ATS128 datasheet(12/25 Pages) ALLEGRO

12 / 25 page

Highly Programmable, Back-Biased,

Hall-Effect Switch with TPOS Functionality

ATS128LSE

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

Overview

Programming is accomplished by sending a series of input volt-

age pulses serially through the VCC (supply) pin of the device.

A unique combination of different voltage level pulses controls

the internal programming logic of the device to select a desired

programmable parameter and change its value. There are three

voltage levels that must be taken into account when program-

ming. These levels are referred to as high (VPH), mid (VPM), and

low (VPL).

The ATS128 features three programmable modes, Try mode,

Blow mode, and Read mode:

• In Try mode, programmable parameter values are set and mea-

sured simultaneously. A parameter value is stored temporarily,

and reset after cycling the supply voltage.

• In Blow mode, the value of a programmable parameter may

be permanently set by blowing solid-state fuses internal to the

device. Device locking is also accomplished in this mode.

• In Read mode, each bit may be verified as blown or not blown.

The programming sequence is designed to help prevent the device

from being programmed accidentally; for example, as a result of

noise on the supply line. Note that, for all programming modes, no

parameter programming registers are accessible after the device-

level LOCK bit is set. The only function that remains accessible is

the overall Fuse Checking feature.

Although any programmable variable power supply can be used

to generate the pulse waveforms, for design evaluations, Allegro

highly recommends using the Allegro Sensor IC Evaluation Kit,

available on the Allegro website On-line Store. The manual for

that kit is available for download free of charge, and provides

additional information on programming these devices. (Note: This

kit is not recommended for production purposes.)

Definition of Terms

The section of the programming logic that controls the

choice of programmable modes and parameters.

Bit Field

The internal fuses unique to each register, represented

as a binary number. Changing the bit field settings of a particular

Programming Guidelines

Table 1. Programming Pulse Requirements, Protocol at TA = 25°C

Characteristics

Symbol

Notes

Min.

Typ.

Max.

Unit

Programming Voltage

VPL

Measured at the VCC pin

4.5

5.5

VPM

12.5

–

VPH

21–27

Programming Current

IPP

VCC = 5 → 26 V, CBLOW = 0.1 μF (min); minimum supply current required to

ensure proper fuse blowing.

175

–

Pulse Width

tLOW

Duration of VPL separating pulses at VPM or VPH

–

μs

tACTIVE

Duration of pulses at VPM or VPH for key/code selection

–

μs

tBLOW

Duration of pulse at VPH for fuse blowing

100

–

μs

Pulse Rise Time

tPr

VPL to VPM or VPL to VPH

–

100

μs

Pulse Fall Time

tPf

VPM to VPL or VPH to VPL

–

100

μs

Blow Pulse Slew Rate

SRBLOW

0.375

–

V/μs

Figure 6. Programming pulse definitions (see table 1)

GND

(Supply

cycled)

Programming

pulses

Blow

pulse

tACTIVE

tLOW

tBLOW

tPr

tPf

VPH

VPM

VPL

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