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ATS128 Datasheet(PDF) 23 Page - Allegro MicroSystems

Part # ATS128
Description  Highly Programmable, Back-Biased, Hall-Effect Switch
PDF  25 Pages
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Manufacturer  ALLEGRO [Allegro MicroSystems]
Direct Link  http://www.allegromicro.com
Logo ALLEGRO - Allegro MicroSystems

ATS128 Datasheet(HTML) 23 Page - Allegro MicroSystems

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Highly Programmable, Back-Biased,
Hall-Effect Switch with TPOS Functionality
ATS128LSE
23
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
The device must be operated below the maximum junction
temperature of the device, TJ(max) . Under certain combina-
tions of peak conditions, reliable operation may require derating
supplied power or improving the heat dissipation properties of
the application. This section presents a procedure for correlating
factors affecting operating TJ. (Thermal data is also available on
the Allegro MicroSystems website.)
The Package Thermal Resistance, RJA, is a figure of merit sum-
marizing the ability of the application and the device to dissipate
heat from the junction (die), through all paths to the ambient air.
Its primary component is the Effective Thermal Conductivity,
K, of the printed circuit board, including adjacent devices and
traces. Radiation from the die through the device case, RJC, is
relatively small component of RJA. Ambient air temperature,
TA, and air motion are significant external factors, damped by
overmolding.
The effect of varying power levels (Power Dissipation, PD), can
be estimated. The following formulas represent the fundamental
relationships used to estimate TJ, at PD.
PD = VIN
× IIN
(1)

T = PD
× RJA
(2)
TJ = TA + ΔT
(3)
For example, given common conditions such as: TA= 25°C,
VIN = 12 V, IIN = 4 mA, and RJA = 140 °C/W, then:
PD = VIN
× IIN = 12 V × 4 mA = 48 mW
T = PD
× RJA = 48 mW × 140 °C/W = 7°C
TJ = TA + T = 25°C + 7°C = 32°C
A worst-case estimate, PD(max) , represents the maximum allow-
able power level, without exceeding TJ(max) , at a selected RJA
and TA.
Example: Reliability for VCC at TA=150°C, package SE, using a
single-layer PCB.
Observe the worst-case ratings for the device, specifically:
RJA=101 °C/W, TJ(max) =165°C, VCC(max) =24V, and
ICC(max) = 5.5 mA.
Calculate the maximum allowable power level, PD(max) . First,
invert equation 3:
Tmax = TJ(max) – TA = 165°C–150°C = 15°C
This provides the allowable increase to TJ resulting from internal
power dissipation. Then, invert equation 2:
PD(max) = Tmax÷RJA =15°C÷101 °C/W= 149mW
Finally, invert equation 1 with respect to voltage:
VCC(est) = PD(max) ÷ ICC(max) = 149 mW÷5.5mA= 27 V
The result indicates that, at TA, the application and device can
dissipate adequate amounts of heat at voltages ≤VCC(est) .
Compare VCC(est) to VCC(max) . If VCC(est) ≤ VCC(max) , then
reliable operation between VCC(est) and VCC(max) requires
enhanced RJA. If VCC(est) ≥ VCC(max) , then operation
between VCC(est) and VCC(max) is reliable under these condi-
tions.
Power Derating



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