OPA693IDBVT datasheet(22/32 Pages) TI1

22 / 32 page

OPA693

SBOS285A

www.ti.com

BOARD LAYOUT GUIDELINES

Achieving optimum performance with a high-frequency amplifier

like the OPA693 requires careful attention to PC board layout

parasitics and external component types. Recommendations

that will optimize performance include:

a) Minimize parasitic capacitance to any AC ground for all

of the signal I/O pins. Parasitic capacitance on the output can

cause instability; on the noninverting input, it can react with the

source impedance to cause unintentional bandlimiting. To

reduce unwanted capacitance, create a window around the

signal I/O pins in all of the ground and power planes around

those pins. Otherwise, ground and power planes should be

unbroken elsewhere on the board.

b) Minimize the distance (< 0.25”) from the power supply pins

to high frequency 0.1

µF decoupling capacitors. At the device

pins, the ground and power plane layout should not be in close

proximity to the signal I/O pins. Avoid narrow power and ground

traces to minimize inductance between the pins and the decou-

pling capacitors. The power supply connections should always

be decoupled with these capacitors. Larger (2.2

µF to 6.8µF)

decoupling capacitors, effective at lower frequency, should also

be used on the supply pins. These may be placed somewhat

farther from the device and may be shared among several

devices in the same area of the PC board.

c) Careful selection and placement of external compo-

nents will preserve the high frequency performance of the

OPA693. Use resistors that have low reactance at high

frequencies. Surface-mount resistors work best and allow a

tighter overall layout. Metal film and carbon composition axi-

ally-leaded resistors can also provide good high-frequency

performance. Again, keep their leads and PC board trace

length as short as possible. Never use wirewound type resis-

tors in a high-frequency application. Since the output pin and

inverting input pin are the most sensitive to parasitic capaci-

tance, always position the series output resistor, if any, as

close as possible to the output pin. Since the inverting input

node is internal for the OPA693, it is more robust to layout

issues than amplifiers with similar speed but external feedback

and gain resistors. Other network components, such as

noninverting input termination resistors, should also be placed

close to the package. Good axial metal film or surface mount

resistors have approximately 0.2pF in shunt with the resistor.

For resistor values > 2.0k

Ω, this parasitic capacitance can add

a pole and/or zero below 400MHz that can effect circuit

operation. Keep resistor values as low as possible consistent

with load driving considerations.

d) Connections to other wideband devices on the PC board

may be made with short direct traces or through onboard

transmission lines. For short connections, consider the trace

and the input to the next device as a lumped capacitive load.

Relatively wide traces (50 to 100mils) should be used, prefer-

ably with ground and power planes opened up around them.

Estimate the total capacitive load and set RS from the plot of

Recommended RS vs Capacitive Load. Low parasitic capacitive

loads (< 4pF) may not need an RS since the OPA693 is

nominally compensated to operate with a 2pF parasitic load. If

a long trace is required, and the 6dB signal loss intrinsic to a

doubly-terminated transmission line is acceptable, implement a

matched impedance transmission line using microstrip or stripline

techniques (consult an ECL design handbook for microstrip and

stripline layout techniques). A 50

Ω environment is normally not

necessary on board, and in fact, a higher impedance environ-

ment will improve distortion, as shown in the distortion versus

load plots. With a characteristic board trace impedance defined

based on board material and trace dimensions, a matching

series resistor into the trace from the output of the OPA693 is

used, as well as a terminating shunt resistor at the input of the

destination device. Remember also that the terminating imped-

ance will be the parallel combination of the shunt resistor and

the input impedance of the destination device; this total effective

impedance should be set to match the trace impedance. If the

6dB attenuation of a doubly-terminated transmission line is

unacceptable, a long trace can be series-terminated at the

source end only. Treat the trace as a capacitive load in this case

and set the series resistor value as shown in the plot of

Recommended RS vs Capacitive Load. This will not preserve

signal integrity as well as a doubly-terminated line. If the input

impedance of the destination device is low, there will be some

signal attenuation due to the voltage divider formed by the

series output into the terminating impedance.

e) Socketing a high-speed part like the OPA693 is not

recommended. The additional lead length and pin-to-pin

capacitance introduced by the socket can create an extremely

troublesome parasitic network, which can make it almost

impossible to achieve a smooth, stable frequency response.

Best results are obtained by soldering the OPA693 directly

onto the board.

INPUT AND ESD PROTECTION

The OPA693 is built using a very high-speed complementary

bipolar process. The internal junction breakdown voltages are

relatively low for these very small geometry devices. These

breakdowns are reflected in the Absolute Maximum Ratings

table. All device pins are protected with internal ESD protec-

tion diodes to the power supplies, as shown in Figure 16.

These diodes provide moderate protection to input overdrive

voltages above the supplies as well. The protection diodes can

typically support 30mA continuous current. Where higher

currents are possible (for example, in systems with

±15V

supply parts driving into the OPA693), current limiting series

resistors may be added on the noninverting input. Keep this

resistor value as low as possible since high values degrade

both noise performance and frequency response. The invert-

ing input already has a 300

Ω resistor from the external pin to

the internal summing junction for the op amp. This provides

considerable protection for that node.

Figure 16. Internal ESD Protection.

External

–V

Internal

Circuitry

OPA693IDBVT Datasheet(PDF) 22 Page - Texas Instruments

OPA693IDBVT Datasheet(HTML) 22 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL