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OPA682 Datasheet(PDF) 6 Page - Texas Instruments |
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OPA682 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 21 page ![]() 6 ® OPA682 ABSOLUTE MAXIMUM RATINGS Power Supply .............................................................................. ±6.5VDC Internal Power Dissipation(1) ............................ See Thermal Information Differential Input Voltage .................................................................. ±1.2V Input Voltage Range ............................................................................ ±V S Storage Temperature Range: P, U, N ........................... –40 °C to +125°C Lead Temperature (soldering, 10s) .............................................. +300 °C Junction Temperature (TJ ) ........................................................... +175°C NOTE:: (1) Packages must be derated based on specified θ JA. Maximum TJ must be observed. PACKAGE DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT PRODUCT PACKAGE NUMBER(1) RANGE MARKING NUMBER(2) MEDIA OPA682P 8-Pin Plastic DIP 006 –40 °C to +85°C OPA682P OPA682P Rails OPA682U SO-8 Surface Mount 182 –40 °C to +85°C OPA682U OPA682U Rails " """" OPA682U/2K5 Tape and Reel OPA682N 6-Lead SOT23 332 –40 °C to +85°C A82 OPA682N/250 Tape and Reel "" " " OPA682N/3K Tape and Reel NOTES: (1) For detailed drawing and dimension table, please see end of data sheet. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of “OPA682U/2K5” will get a single 2500-piece Tape and Reel. PACKAGE/ORDERING INFORMATION ELECTROSTATIC DISCHARGE SENSITIVITY Electrostatic discharge can cause damage ranging from perfor- mance degradation to complete device failure. Burr-Brown Corpo- ration recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. PIN CONFIGURATION Top View DIP/SO-8 1 2 3 6 5 4 Output –V S +IN +V S DIS –IN R F 400 Ω R G 400 Ω 12 3 65 4 A82 Pin Orientation/Package Marking 1 2 3 4 8 7 6 5 DIS +V S Output NC RF 400 Ω RG 400 Ω NC –IN +IN –V S NC: No Connection Top View SOT23-6 |
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