VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC8162

2.488 Gbit/sec SONET/SDH

1:16 Demux with Clock Recovery

Page 8

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

9/14/98

G52209-0, Rev. 2.0

D[0-15]+/-, PARITY+/-, CLK16+/- Outputs:

The D[0:15]+/-, PARITY+/-, and CLK16+/- output drivers are special-purpose output drivers designed for

low power dissipation. Four possible termination schemes are shown in Figures 6, 7, 8, and 9.

Figures 6 and 7 are the preferred termination methods. Figure 6 indicates a DC-differential termination

method, and Figure 7 is true differential termination. For interfacing the VSC8162 device directly to a

VSC8161, Figure 6 is preferred since the DC differential method does not force a DC common mode level at

the receiver. The VSC8161 input receivers have internal DC bias resistor that allow them to set their own DC

bias level.

Figure 6: Low-Speed Output Termination #1

Figure 7: Low-Speed Output Termination #2

8162

0.1

µF

50

Ω

50

Ω

Receiving Device

0.1

µF

0.1

µF

8162

0.1

µF

0.1

µF

100

Ω

Receiving Device