VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC8162

2.488 Gbit/sec SONET/SDH

1:16 Demux with Clock Recovery

Page 4

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

9/14/98

G52209-0, Rev. 2.0

Figure 1: Retiming Offset

1:16 Demultiplexer

The demultiplexer inside of the VSC8162 consists of a 1:16 demultiplexer and timing circuitry which gen-

erates a divide-by-16 clock from the high speed clock input. The demultiplexer accepts a serial data stream

input (DI+/DI-) at 2.488 Gb/s and deserializes it into 16 parallel differential outputs (D0..D15). The timing

parameters of the parallel data outputs (D0..D15) are specified with respect to the falling edge of CLK16, so

that CLK16 can be used to clock the destination of D0..D15.

The parity output of the demultiplexer is the XOR of all 16 parallel outputs. The DINVERT input is an ECL

input (see Table 6) which can be used to invert the sense of the data through the demultiplexer. If DINVERT is

left floating, it defaults to the low state, which is the state that corresponds to normal operation (no data inver-

sion).

FILTI, FILTO Pins

The FILTI and FILTO pins are used to provide additional capacitance to the loop filter of the VCO. To opti-

mize the VCO’s performance, it is recommended that 0.1

µF, size 0805 capacitors are connected between the

FILTI+ and FILTI- pins, as well as the FILTO+ and FILTO- pins.

Supplies

the part can be operated in an all positive supply environment, or a mixed positive and negative supply environ-

ment.

To operate in an all positive supply environment, each of the supply voltages must be shifted up by 5.2V

Bear in mind that termination voltages must be adjusted to reflect any shift in supply voltages.

Sampling point at the

center of the eye

Sampling point

delayed ~50ps from

the center of the eye

PH_ADJ[4:0] = 00100

DI

PH_ADJ[4:0] = 00000