5-126
RF2705
Rev A4 041026
Pin
Function
Description
Interface Schematic
8Q SIG N
Quadrature Q channel negative baseband input port.
Best performance is achieved when the QSIGP and QSIGN are driven
differentially with a 1.2V common mode DC voltage. The recom-
mended differential drive level (VQSIGP-VQSIGN) is 1.2VP-P for EDGE,
0.8VP-P for W-CDMA modulation and 1.0VP-P for GMSK modulation.
This input should be DC-biased at 1.2V. In sleep mode an internal FET
switch is opened, the input goes high impedance and the modulator is
de-biased.
Phase or amplitude errors between the QSIGP and QSIGN signals will
result in a common-mode signal which may result in an increase in the
even order distortion of the modulation in the output spectrum.
DC offsets between the QSIGP and QSIGN signals will result in
increased carrier leakage. Small DC offsets may be deliberately
applied between the ISIGP/ISIGN and QSIGP/QSIGN inputs to can-
cel out the LO leakage. The optimum corrective DC offsets will change
with mode, frequency and gain control.
Common-mode noise on the QSIGP and QSIGN should be kept low
as it may degrade the noise performance of the modulator.
Phase offsets from quadrature between the I and Q baseband signals
results in degraded sideband suppression.
9Q SIG P
Quadrature Q channel negative baseband input port. See pin 8.
See pin 8.
10
VREF
Voltage reference decouple.
External 10nF decoupling capacitor to ground.
The voltage on this pin is typically 1.67V when the chip is enabled. The
voltage is 0V when the chip is powered down.
The purpose of this decoupling capacitor is to filter out low frequency
noise (20MHz) on the gain control lines.
Poor positioning of the VREF decoupling capacitor can cause a degra-
dation in LO leakage.
A voltage of around 2.5V on this pin indicates that the die flag under
the chip is not grounded and the chip is not biased correctly.
11
GC DEC
Gain control voltage decouple with an external 1nF decoupling capaci-
tor to ground.
The voltage on this pin is a function of gain control (GC) voltage when
the chip is enabled. The voltage is 0V when the chip is powered down.
The purpose of this decoupling capacitor is to filter out low frequency
noise (20MHz) on the gain control lines. The size capacitor on the GC
DEC line will effect the settling time response to a step in gain control
voltage. A 1nF capacitor equates to around 200ns settling time and a
0.5nF capacitor equates to a 100ns settling time. There is a trade-off
between settling time and noise contributions by the gain control cir-
cuitry as gain control is applied.
Poor positioning of the VREF decoupling capacitor can cause a degra-
dation in LO leakage.
12
GC
Gain control voltage. Maximum output power at 2.0V. Minimum output
power at 0V. When the chip is enabled the input impedance is 10k
Ω to
1.67VDC. When the chip is powered down a FET switch is opened and
the input goes high impedance.
V
CC2
x1
V
CC2
-
+
4 k
Ω
V
CC2
-
+
4 k
Ω
V
CC2
-
+
4 k
Ω
10 k
Ω
1.7 V
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