GXM datasheet(42/244 Pages) NSC

42 / 244 page

www.national.com

Revision 3.1

Processor Programming (Continued)

3.3.1.2

Segment Registers

The 16-bit segment registers, part of the main memory

addressing mechanism, are described in Section 3.5 “Off-

set, Segment, and Paging Mechanisms” on page 61. The

six segment registers are:

Code Segment

Data Segment

Stack Segment

Extra Segment

Additional Data Segment

The segment registers are used to select segments in

main memory. A segment acts as private memory for dif-

ferent elements of a program such as code space, data

space, and stack space.

There are two segment mechanisms, one for real and vir-

tual 8086 operating modes and one for protective mode.

Initialization and transition to protective mode is described

in Section 3.13.4 “Initialization and Transition to Protected

Mode” on page 87. The segment mechanisms are

described in Section 3.7 “Descriptors and Segment Mech-

anisms” on page 62.

The active segment register is selected according to the

ruleslistedinTable 3-3and thetypeofinstruction being

currently processed. In general, the DS register selector is

used for data references. Stack references use the SS

some of these selections may be overridden, instruction

fetches, stack operations, and the destination write opera-

tion of string operations cannot be overridden. Special

segment-override instruction prefixes allow the use of

alternate segment registers. These segment registers

include the ES, FS, and GS registers.

3.3.1.3

Instruction Pointer Register

The Instruction Pointer (EIP) Register contains the off-

set into the current code segment of the next instruction to

be executed. The register is normally incremented by the

length of the current instruction with each instruction exe-

cution unless it is implicitly modified through an interrupt,

exception, or an instruction that changes the sequential

execution flow (for example JMP and CALL).

Table 3-3 illustrates the code segment selection rules.

Table 3-3. Segment Register Selection Rules

Type of Memory Reference

Implied (Default)

Segment

Segment-Override

Prefix

Code Fetch

None

Destination of PUSH, PUSHF, INT, CALL, PUSHA instructions

None

Source of POP, POPA, POPF, IRET, RET instructions

None

Destination of STOS, MOVS, REP STOS, REP MOVS instructions

None

Other data references with effective address using base registers of:

EAX, EBX, ECX, EDX, ESI, EDI, EBP, ESP

CS,ES, FS,GS, SS

CS, DS, ES, FS, GS

GXM Datasheet(PDF) 42 Page - National Semiconductor (TI)

GXM Datasheet(HTML) 42 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL