GXM datasheet(25/244 Pages) NSC

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Signal Definitions (Continued)

INTR

B18

D24

(Maskable) Interrupt Request

INTR is a level-sensitive input that causes the GXm processor to

Suspend execution of the current instruction stream and begin

execution of an interrupt service routine. The INTR input can be

masked through the Flags Register IF bit. (See Table 3-4 on

page 43 for bit definitions.)

IRQ13

C22

C31

Interrupt Request Level 13

IRQ13 is asserted if an on-chip floating point error occurs.

When a floating point error occurs, the GXm processor asserts

the IRQ13 pin. The floating point interrupt handler then performs

an OUT instruction to I/O address F0h or F1h. The GXm proces-

sor accepts either of these cycles and clears the IRQ13 pin.

Refer to Section 3.4.1 “I/O Address Space” on page 60 for fur-

ther information on IN/OUT instructions.

SMI#

C19

B28

System Management Interrupt

SMI# is a level-sensitive interrupt. SMI# puts the GXm processor

into System Management Mode (SMM).

SUSP#

(PU)

Suspend Request

This signal is used to request that the GXm processor enter Sus-

pend mode. After recognition of an active SUSP# input, the pro-

cessor completes execution of the current instruction, any

pending decoded instructions and associated bus cycles.

SUSP# is ignored following RESET# and is enabled by setting

the SUSP bit in CCR2. (See Table 16 on page 44 for CCR2 bit

definitions.)

Since the GXm processor includes system logic functions as well

as the CPU core, there are special modes designed to support

the different power management states associated with APM,

ACPI, and portable designs. The part can be configured to stop

only the CPU core clocks, or all clocks. When all clocks are

stopped, the external clock can also be stopped. (See Section

6.0 “Power Management” on page 174 for more details regarding

power management states.)

This pin is internally connected to a 20-kohm pull-up resistor.

SUSP# is pulledupwhennot active.

SUSPA#

Suspend Acknowledge

Suspend Acknowledge indicates that the GXm processor has

entered low-power Suspend mode as a result of SUSP# asser-

tion or execution of a HALT instruction. SUSPA# is enabled by

setting the SUSP bit in CCR2. (See Table 16 on page 44 for

CCR2 bit definitions.)

The SYSCLK input may be stopped after SUSPA# has been

asserted to further reduce power consumption if the system is

configured for 3V Suspend mode. (Section 6.4 “3-Volt Suspend

Mode” on page 174 for details regarding this mode.)

SERIALP

Serial Packet

Serial Packet is the single wire serial-transmission signal to the

CS5530 chip. The clock used for this interface is the PCI clock

(SYSCLK). This interface carries packets of miscellaneous infor-

mation to the chipset to be used by the VSA software handlers.

2.2.1

System Interface Signals (Continued)

Signal Name

BGA

Pin No.

SPGA

Pin No.

Type

Description

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