GXM datasheet(226/244 Pages) NSC

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Instruction Set (Continued)

FCOS Function Evaluation: Cos(x)

D9 FF

TOS <--- COS(TOS)

92 - 141

FDECSTP Decrement Stack pointer

D9 F6

Decrement top of stack pointer

FDIV Floating Point Divide

Top of Stack

DC [1111 1 n]

ST(n) <--- ST(n) / TOS

24 - 34

80-bit Register

D8 [1111 0 n]

TOS <--- TOS / ST(n)

24 - 34

64-bit Real

DC [mod 110 r/m]

TOS <--- TOS / M.DR

24 - 34

32-bit Real

D8 [mod 110 r/m]

TOS <--- TOS / M.SR

24 - 34

FDIVP Floating Point Divide, Pop

DE [1111 1 n]

ST(n) <--- ST(n) / TOS; then pop TOS

24 - 34

FDIVR Floating Point Divide Reversed

Top of Stack

DC [1111 0 n]

TOS <--- ST(n) / TOS

24 - 34

80-bit Register

D8 [1111 1 n]

ST(n) <--- TOS / ST(n)

24 - 34

64-bit Real

DC [mod 111 r/m]

TOS <--- M.DR / TOS

24 - 34

32-bit Real

D8 [mod 111 r/m]

TOS <--- M.SR / TOS

24 - 34

FDIVRP Floating Point Divide Reversed, Pop

DE [1111 0 n]

ST(n) <--- TOS / ST(n); then pop TOS

24 - 34

FIDIV Floating Point Integer Divide

32-bit Integer

DA [mod 110 r/m]

TOS <--- TOS / M.SI

34 - 38

16-bit Integer

DE [mod 110 r/m]

TOS <--- TOS / M.WI

34 - 38

FIDIVR Floating Point Integer Divide Reversed

32-bit Integer

DA [mod 111 r/m]

TOS <--- M.SI / TOS

34 - 38

16-bit Integer

DE [mod 111 r/m]

TOS <--- M.WI / TOS

34 - 38

FFREE Free Floating Point Register

DD [1100 0 n]

TAG(n) <--- Empty

FINCSTP Increment Stack Pointer

D9 F7

Increment top-of-stack pointer

FINIT Initialize FPU

(9B)DB E3

Wait, then initialize

FNINIT Initialize FPU

DB E3

Initialize

FLD Load Data to FPU Register

Top of Stack

D9 [1100 0 n]

Push ST(n) onto stack

64-bit Real

DD [mod 000 r/m]

Push M.DR onto stack

32-bit Real

D9 [mod 000 r/m]

Push M.SR onto stack

FBLD Load Packed BCD Data to FPU Register

DF [mod 100 r/m]

Push M.BCD onto stack

41 - 45

FILD Load Integer Data to FPU Register

64-bit Integer

DF [mod 101 r/m]

Push M.LI onto stack

4 - 8

32-bit Integer

DB [mod 000 r/m]

Push M.SI onto stack

4 - 6

16-bit Integer

DF [mod 000 r/m]

Push M.WI onto stack

3 - 6

FLD1 Load Floating Const.= 1.0

D9 E8

Push 1.0 onto stack

FLDCW Load FPU Mode Control Register

D9 [mod 101 r/m]

Ctl Word <--- Memory

FLDENV Load FPU Environment

D9 [mod 100 r/m]

Env Regs <--- Memory

FLDL2E Load Floating Const.= Log2(e)

D9 EA

Push Log2(e) onto stack

FLDL2T Load Floating Const.= Log2(10)

D9 E9

Push Log2(10) onto stack

FLDLG2 Load Floating Const.= Log10(2)

D9 EC

Push Log10(2) onto stack

FLDLN2 Load Floating Const.= Ln(2)

D9 ED

Push Loge(2) onto stack

FLDPI Load Floating Const.=

D9 EB

Push

π onto stack

FLDZ Load Floating Const.= 0.0

D9 EE

Push 0.0 onto stack

FMUL Floating Point Multiply

TopofStack

DC [11001 n]

ST(n)<--- ST(n)

× TOS

4 - 9

80-bit Register

D8 [1100 1 n]

TOS <--- TOS

× ST(n)

4 - 9

64-bit Real

DC [mod 001 r/m]

TOS <--- TOS

× M.DR

4 - 8

32-bit Real

D8 [mod 001 r/m]

TOS <--- TOS

× M.SR

4 - 6

FMULP Floating Point Multiply & Pop

DE [1100 1 n]

ST(n) <--- ST(n)

× TOS; then pop TOS

4 - 9

FIMUL Floating Point Integer Multiply

32-bit Integer

DA [mod 001 r/m]

TOS <--- TOS

× M.SI

9 - 11

16-bit Integer

DE [mod 001 r/m]

TOS <--- TOS

× M.WI

8 - 10

Table 9-29. FPU Instruction Set Summary (Continued)

FPU Instruction

Opcode

Operation

Clock

Count

Notes

GXM Datasheet(PDF) 226 Page - National Semiconductor (TI)

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