TSB42AB4 datasheet(46/183 Pages) TI

46 / 183 page

3−21

ceLynx always generates the clock at the SCL line. The data at the SDA line has to be changed in the low

phase of the clock only. Changing the SDA line in the clock-high-phase is interpreted as start- or

stop-condition.

The first byte sent by ceLynx is the device address of the EEPROM. The data transfer begins with 8 bits

of data and a 1-bit ACK. The ACK is given by the receiving unit. ceLynx generates a stop-condition to end

the communication.

Start/Stop-Condition

SDA

Timing: Data-Transfer and Acknowledge

Start-

Condition

Stop-

Condition

SCL

SCL from Master

Data from Transmitter

Data from Receiver

ACK

LSB

MSB

Figure 3−26. Two-Wire Serial Interface Bus Protocol

3.4.2

ceLynx/Two-Wire Serial-Interface EEPROM Protocol

Definitions:

MASTER: ceLynx

SLAVE:

EEPROM

0 1

0 0 d

Read (1)

Write (0)

MSB

LSB

Device-Address Format

Figure 3−27. EEPROM Protocol Device Address Format

This operation sets the internal address counter of the EEPROM. Any read operation after that starts at the

specified address.

Start

1 0

0 0 0

Device-Address

and Read

1st data byte

2nd data byte

nth (last) data byte

Slave

Master

ACK

read

ACK

Stop

no ACK

Typical Read Operation

Figure 3−28. EEPROM Protocol Typical Read Operation

TSB42AB4 Datasheet(PDF) 46 Page - Texas Instruments

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