TSB42AB4 datasheet(90/183 Pages) TI

90 / 183 page

5−25

The user should not enable the insert packet control token on receive.

Either the host or HSDI can access the data buffer. The host can access the data

buffer through the DB(N)ACC0 register for the associated buffer.

5.5.5

DV Transmit

For DV transmit, ceLynx can be configured to include any of the four 1394 DV headers. The

TXDP(N)CFG.HIM

control

bit

automatically

inserts

the

necessary

headers

specified

DB(N)CFG0.STREAMTYPE.

ceLynx

automatically

inserts

the

DIF

block

header

the

TXDP(N)CFG.H0IM bit is selected.

Table 5−22. DV TX Headers

DV TRANSMIT

PACKET HEADERS

REGISTERS USED TO

INSERT HEADERS

DEFAULT VALUES

FOR DV TX

ISO HEADER

TXDP(N)H0

0008 40A0

CIP0

TXDP(N)H1

0078 0000

CIP1

TXDP(N)H2

8000 FFFF

DV_H0

TXDP(N)H3

0000 0000

DV_H1

TXDP(N)H4

0000 0000

NOTE:

The application must supply quadlet-aligned data in DV transmit mode. No padding

bits is added.

The host can access the data buffer through the DB(N)ACC0 and DB(N)ACC1

registers for the associated buffer. The host should write all transmit quadlets

except the last to the DB(N)ACC0 register. The host should write the last transmit

quadlet to the DB(N)ACC1 register.

5.6

PHY Configuration Packet

The format of the PHY configuration packet is shown in Figure 5−27 and is described in Table 5−26. The

PHY configuration packet transmit contains two quadlets, which are loaded into the selected data buffer.

The default data buffer for asynchronous transmit is buffer 4 and is accessed by the microprocessor. The

first quadlet is written to the DB(N)ACC0 register for the appropriate data buffer. The last quadlet is written

to the DB(N)ACC1 register for the appropriate data buffer. The 0x00E0 in the first quadlet tells ceLynx that

this quadlet is the PHY configuration packet. The 0xE is then replaced with 0x0 before the packet is

transmitted to the PHY interface.

ROOT_ID

30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

GAP_CNT

logical inverse of first 16 bits of first quadlet

1 1

111

11 1 1

Figure 5−25. PHY Configuration Packet Format

TSB42AB4 Datasheet(PDF) 90 Page - Texas Instruments

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