DA9062 datasheet(32/93 Pages) DIALOG

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DA9062

Entry level PMIC for applications requiring up to 8.5 A

Datasheet

Revision 3.2

18-Feb-2015

32 of 93

7.1.3

nRESET

nRESET is an active-low reset output intended for resetting the host processor of the system. The

signal can be configured as either push-pull or open drain output (PM_O_TYPE).

nRESET is always asserted upon a cold boot from the no-power mode. It is always asserted at the

beginning of a shutdown sequence to the RESET mode. nRESET may also be asserted at the

beginning of the sequence to the POWERDOWN mode, if configured in nRES_MODE.

De-assertion of nRESET is controlled by a reset timer. After being asserted, nRESET remains low

until the reset timer, which was started from the selected trigger signal, expires. The reset timer

trigger can be selected via RESET_EVENT and set to one of the following: an external signal

triggering the wakeup (EXT_WAKEUP), an internal signal indicating the end of the first power-up

sub-sequence (SYS_UP), an internal signal indicating the end of the second power-up sub-sequence

(PWR_UP), or the transition of DA9062 from reset to POWERDOWN mode. The expiry time can be

configured via RESET_TIMER from 1 ms to 1 s. If RESET_TIMER is set to 0 ms, nRESET is de-

asserted immediately after the trigger selected with RESET_EVENT.

7.1.4

nIRQ

nIRQ is a level-sensitive interrupt signal. It can be configured either as a push-pull or an open drain

output (selected via PM_O_TYPE). The polarity of nIRQ can be selected with IRQ_TYPE.

nIRQ is asserted when an unmasked event has occurred. The nIRQ will not be released until all

event registers have been cleared. New events that occur while reading an event register are saved

until the event register is cleared, ensuring that the host processor captures them. The same will

happen to all events occurring when the power sequencer is in transition.

7.2

2-wire interface

The 2-wire interface provides access to the control and status registers. The interface supports

operations compatible to the standard, fast, fast-plus, and high-speed modes of the I

2C bus

specification Rev. 3. Communication on the 2-wire bus is always between two devices; one acting as

the master and the other as the slave. The DA9062 only operates as a slave.

SCL transmits 2-wire clock data and SDA transmits the bidirectional data. The 2-wire interface is

open-drain supporting multiple devices on one line. The bus lines have to be pulled high by an

external pull-up resistor (2 to 20

kΩ). The attached devices drive the bus lines low by connecting

them to ground. As a result, two devices can drive the bus simultaneously without conflict. In

standard/fast mode the highest frequency of the bus is 400 kHz. The exact frequency can be

determined by the application and it does not have any relation to the DA9062 internal clock signals.

DA9062 stays within the described host clock speed limitations and does not initiate clock slow-

down. An automatic interface reset is triggered when the clock signal ceases toggling for >35 ms

(controlled in TWOWIRE_TO).

When the SDA is stuck, the bus clears after receiving nine clock pulses. Operation in high-speed

mode at 3.4 MHz requires a minimum interface supply voltage of 1.8 V and a mode change in order

to enable slope-control. The high-speed mode can be enabled on a transfer-by-transfer basis by

sending the master code (0000 1XXX) at the beginning of the transfer. The DA9062 does not make

use of clock stretching and delivers read data without delay up to 3.4 MHz.

Alternatively, the interface can be configured to use high-speed mode continuously via PM_IF_HSM,

so that the master code is not required at the beginning of every transfer. This reduces

communication overhead on the bus and limits the attachable bus slaves to compatible devices.

DA9062 Datasheet(PDF) 32 Page - Dialog Semiconductor

DA9062 Datasheet(HTML) 32 Page - Dialog Semiconductor

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