DA14583 datasheet(86/148 Pages) DIALOG

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Target - March 06, 2015 v1.1

7:0

R/W

SRBR_STHRX

Shadow Receive Buffer Register x: This is a shadow register

for the RBR and has been allocated sixteen 32-bit locations

so as to accommodate burst accesses from the master. This

port (sin) in UART mode or the serial infrared input (sir_in) in

infrared mode. The data in this register is valid only if the Data

Ready (DR) bit in the Line status Register (LSR) is set. If

FIFOs are disabled (FCR[0] set to zero), the data in the RBR

must be read before the next data arrives, otherwise it will be

overwritten, resulting in an overrun error. If FIFOs are enabled

(FCR[0] set to one), this register accesses the head of the

receive FIFO. If the receive FIFO is full and this register is not

read before the next data character arrives, then the data

already in the FIFO will be preserved but any incoming data

will be lost. An overrun error will also occur. Shadow Transmit

Holding Register 0: This is a shadow register for the THR and

has been allocated sixteen 32-bit locations so as to accom-

modate burst accesses from the master. This register con-

tains data to be transmitted on the serial output port (sout) in

UART mode or the serial infrared output (sir_out_n) in infra-

red mode. Data should only be written to the THR when the

THR Empty (THRE) bit (LSR[5]) is set. If FIFO's are disabled

(FCR[0] set to zero) and THRE is set, writing a single charac-

ter to the THR clears the THRE. Any additional writes to the

THR before the THRE is set again causes the THR data to be

overwritten. If FIFO's are enabled (FCR[0] set to one) and

THRE is set, x number of characters of data may be written to

the THR before the FIFO is full. The number x (default=16) is

determined by the value of FIFO Depth that you set during

configuration. Any attempt to write data when the FIFO is full

results in the write data being lost.

0x0

Table 123: UART2_SRBR_STHR10_REG (0x50001158)

Bit

Mode

Symbol

Description

Reset

Table 124: UART2_SRBR_STHR11_REG (0x5000115C)

Bit

Mode

Symbol

Description

Reset

15:8

Reserved

0x0

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