DA14583 datasheet(39/148 Pages) DIALOG

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Target - March 06, 2015 v1.1

R/W

ETBEI_DLH1

Interrupt Enable Register: ETBEI, Enable Transmit Holding

generation of Transmitter Holding Register Empty Interrupt.

This is the third highest priority interrupt. 0 = disabled 1 = ena-

bled Divisor Latch (High): Bit[1] of the 8 bit DLH register.

0x0

R/W

ERBFI_DLH0

Interrupt Enable Register: ERBFI, Enable Received Data

Available Interrupt. This is used to enable/disable the genera-

tion of Received Data Available Interrupt and the Character

Timeout Interrupt (if in FIFO mode and FIFO's enabled).

These are the second highest priority interrupts. 0 = disabled

1 = enabled Divisor Latch (High): Bit[0] of the 8 bit DLH regis-

ter.

0x0

Table 64: UART_IER_DLH_REG (0x50001004)

Bit

Mode

Symbol

Description

Reset

Table 65: UART_IIR_FCR_REG (0x50001008)

Bit

Mode

Symbol

Description

Reset

15:0

R/W

IIR_FCR

Interrupt Identification Register, reading this register; FIFO

Control Register, writing to this register. Interrupt Identification

to indicate whether the FIFO's are enabled or disabled. 00 =

disabled. 11 = enabled. Bits[3:0], Interrupt ID (or IID): This

indicates the highest priority pending interrupt which can be

one of the following types: 0000 = modem status. 0001 = no

interrupt pending. 0010 = THR empty. 0100 = received data

available. 0110 = receiver line status. 0111 = busy detect.

1100 = character timeout. Bits[7:6], RCVR Trigger (or RT):.

This is used to select the trigger level in the receiver FIFO at

which the Received Data Available Interrupt will be gener-

ated. In auto flow control mode it is used to determine when

the rts_n signal will be de-asserted. It also determines when

the dma_rx_req_n signal will be asserted when in certain

modes of operation. The following trigger levels are sup-

ported: 00 = 1 character in the FIFO 01 = FIFO 1/4 full 10 =

FIFO 1/2 full 11 = FIFO 2 less than full Bits[5:4], TX Empty

Trigger (or TET): This is used to select the empty threshold

level at which the THRE Interrupts will be generated when the

mode is active. It also determines when the dma_tx_req_n

signal will be asserted when in certain modes of operation.

The following trigger levels are supported: 00 = FIFO empty

01 = 2 characters in the FIFO 10 = FIFO 1/4 full 11 = FIFO 1/

2 full Bit[3], DMA Mode (or DMAM): This determines the DMA

signalling mode used for the dma_tx_req_n and

dma_rx_req_n output signals. 0 = mode 0 1 = mode 1 Bit[2],

XMIT FIFO Reset (or XFIFOR): This resets the control portion

of the transmit FIFO and treats the FIFO as empty. Note that

this bit is 'self-clearing' and it is not necessary to clear this bit.

Bit[1], RCVR FIFO Reset (or RFIFOR): This resets the control

portion of the receive FIFO and treats the FIFO as empty.

Note that this bit is 'self-clearing' and it is not necessary to

clear this bit. Bit[0], FIFO Enable (or FIFOE): This enables/

disables the transmit (XMIT) and receive (RCVR) FIFO's.

Whenever the value of this bit is changed both the XMIT and

RCVR controller portion of FIFO's will be reset.

0x0

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