AD15700SLASHPCB datasheet(35/44 Pages) AD

35 / 44 page

REV. A

AD15700

–35–

MICROPROCESSOR INTERFACING

The ADC is ideally suited for traditional dc measurement appli-

cations supporting a microprocessor, and ac signal processing

applications interfacing to a digital signal processor. The ADC is

designed to interface either with a parallel 8-bit or 16-bit wide

interface or with a general-purpose serial port or I/O ports on a

microcontroller. A variety of external buffers can be used with the

ADC to prevent digital noise from coupling into the ADC. The

following sections illustrate the use of the ADC with an SPI

equipped microcontroller, the ADSP-21065L and ADSP-218x

signal processors.

SPI Interface (MC68HC11)

Figure 25 shows an interface diagram between the ADC and an SPI

equipped microcontroller like the MC68HC11. To accommodate

the slower speed of the microcontroller, the ADC acts as a slave

device and data must be read after conversion. This mode also

allows the daisy-chain feature. The convert command could be

initiated in response to an internal timer interrupt. The reading of

output data, one byte at a time, if necessary, could be initiated in

response to the end-of-conversion signal (BUSY going low) using

an interrupt line of the microcontroller. The serial peripheral

interface (SPI) on the MC68HC11 is configured for master mode

(MSTR) = 1, Clock Polarity Bit (CPOL) = 0, Clock Phase Bit

(CPHA) = 1, and SPI Interrupt Enable (SPIE) = 1 by writing

to the SPI Control Register (SPCR). The IRQ is configured for

edge-sensitive-only operation (IRQE = 1 in OPTION register).

AD15700*

BUSY

INVSCLK

SDOUT

CNVST

SCLK

MC68HC11*

IRQ

MSO/SDI

I/O PORT

SCK

*ADDITIONAL PINS OMITTED FOR CLARITY

CS_ADC

EXT/

INT

SER/

PAR

DVDD

Figure 25. Interfacing the AD15700 to SPI Interface

ADSP-21065L in Master Serial Interface

As shown in Figure 26, AD15700s can be interfaced to the

ADSP-21065L using the serial interface in master mode without

any glue logic required. This mode combines the advantages of

reducing the wire connections and the ability to read the data

during or after conversion at maximum speed transfer

(DIVSCLK[0:1] both low).

The ADC is configured for the internal clock mode (EXT/

INT

low) and acts, therefore, as the master device. The convert com-

mand can be generated by either an external low jitter oscillator

or, as shown, by a FLAG output of the ADSP-21065L or by a

frame output TFS of one serial port of the ADSP-21065L,

which can be used like a timer. The serial port on the ADSP-21065L

is configured for external clock (IRFS = 0), rising edge active

(CKRE = 1), external late framed sync signals (IRFS = 0, LAFS = 1,

RFSR = 1), and active high (LRFS = 0). The serial port of the

ADSP-21065L is configured by writing to its receive control

Because the serial port within the ADSP-21065L will be seeing

a discontinuous clock, an initial word reading has to be done

after the ADSP-21065L has been reset to ensure that the serial

port is properly synchronized to this clock during each following

data read operation.

AD15700*

SYNC

INVSCLK

SDOUT

CNVST

SCLK

ADSP-21065L*

SHARC

RFS

FLAG OR TFS

RCLK

*ADDITIONAL PINS OMITTED FOR CLARITY

CS_ADC

RDC/SDIN

SER/

PAR

DVDD

INVSYNC

EXT/

INT

Figure 26. Interfacing to the ADSP-21065L Using

the Serial Master Mode

APPLICATION HINTS

Layout

The AD15700’s ADC has very good immunity to noise on the

power supplies as can be seen in Figure 12. However, care should

still be taken with regard to grounding layout.

The printed circuit board that houses the AD15700 should be

designed so the analog and digital sections are separated and

confined to certain areas of the board. This facilitates the use of

ground planes that can be easily separated. Digital and analog

ground planes should be joined in only one place, preferably

underneath the AD15700, or at least as close as possible to the

AD15700. If the AD15700 is in a system where multiple devices

require analog-to-digital ground connections, the connection should

still be made at one point only, a star ground point, which should

be established as close as possible to the AD15700. It is recom-

mended to avoid running digital lines under the device as these

will couple noise onto the die. The analog ground plane should

be allowed to run under the switching signals like

CNVST or

clocks should be shielded with digital ground to avoid radiating

noise to other sections of the board, and should never run near

analog signal paths. Crossover of digital and analog signals should

be avoided. Traces on different but close layers of the board

should run at right angles to each other. This will reduce the

effect of feedthrough through the board.

The power supply lines to the AD15700 should use as large a trace

as possible to provide low impedance paths and reduce the effect

of glitches on the power supply lines. Good decoupling is also impor-

tant to lower the supply impedance presented to the AD15700

and reduce the magnitude of the supply spikes. Decoupling

ceramic capacitors, typically 100 nF, should be placed on each

power supply pin, AVDD, DVDD, and OVDD, close to and

ideally right up against these pins and their corresponding ground

pins. Additionally, low ESR 10 nF capacitors should be located

in the vicinity of the ADC to further reduce low frequency ripple.

The DVDD supply of the AD15700 can be either a separate supply

or come from the analog supply, AVDD, or from the digital

interface supply, OVDD. When the system digital supply is noisy,

or fast switching digital signals are present, it is recommended if

no separate supply is available to connect the DVDD digital supply

to the analog supply AVDD through an RC filter, and connect

the system supply to the interface digital supply OVDD and the

remaining digital circuitry. When DVDD is powered from the

system supply, it is useful to insert a bead to further reduce high

frequency spikes.

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