AD15700SLASHPCB datasheet(38/44 Pages) AD

38 / 44 page

REV. A

–38–

AD15700

ADSP-2101/ADSP-2103 to DAC Interface

Figure 33 shows a serial interface between the DAC and the

ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should

be set to operate in the SPORT (Serial Port) Transmit Alternate

Framing Mode. The ADSP-2101/ADSP-2103 is programmed

through the SPORT Control Register and should be configured

as follows: internal clock operation, active low framing, 16-bit

word length. The first two bits are DON’T CARE as the DAC

will keep the last 14 bits. Transmission is initiated by writing a

word to the Tx Register after the SPORT has been enabled.

Because of the edge-triggered difference, an inverter is required at

the SCLKs between the DSP and the DAC.

ADSP-2101/

ADSP-2103*

*ADDITIONAL PINS OMITTED FOR CLARITY

CS_DAC

DIN

SCLK

TFS

DAC

Figure 33. ADSP-2101/ADSP-2103 to DAC Interface

68HC11/68L11 to DAC Interface

Figure 34 shows a serial interface between the DAC and the

68HC11/68L11 microcontroller. SCK of the 68HC11/68L11

drives the SCLK of the DAC, while the MOSI output drives the

serial data lines SDIN. CS signal is driven from one of the port lines.

The 68HC11/68L11 is configured for master mode; MSTR = 1,

CPOL = 0, and CPHA = 0. Data appearing on the MOSI

output is valid on the rising edge of SCK.

68HC11/

68L11*

*ADDITIONAL PINS OMITTED FOR CLARITY

CS_DAC

DIN

SCLK

SCK

MOSI

PC7

PC6

DAC

Figure 34. 68HC11/68L11 to DAC Interface

MICROWIRE to DAC Interface

Figure 35 shows an interface between the DAC and any

MICROWIRE compatible device. Serial data is shifted out on

the falling edge of the serial clock and into the DAC on the

rising edge of the serial clock. No glue logic is required as the

DAC clocks data into the input shift register on the rising edge.

MICROWIRE*

*ADDITIONAL PINS OMITTED FOR CLARITY

CS_DAC

DIN

SCLK

DAC

Figure 35. MICROWIRE to DAC Interface

80C51/80L51 to DAC Interface

A serial interface between the DAC and the 80C51/80L51

microcontroller is shown in Figure 36. TxD of the microcontroller

drives the SCLK of the DAC, while RxD drives the serial data line

of the DAC. P3.3 is a bit programmable pin on the serial port

that is used to drive

CS_DAC.

80C51/

80L51*

*ADDITIONAL PINS OMITTED FOR CLARITY

DAC

CS_DAC

DIN

SCLK

TxD

RxD

P3.3

Figure 36. 80C51/80L51 to DAC Interface

The 80C51/80L51 provides the LSB first, while the DAC

expects the MSB of the 14-bit word first. Care should be taken

to ensure the transmit routine takes this into account. Usually it

can be done through software by shifting out and accumulating

the bits in the correct order before inputting to the DAC. Also,

80C51 outputs 2-byte word/16-bit data. Thus the first two bits,

after rearrangement, should be DON’T CARE as they will be

dropped from the DAC’s 14-bit word.

When data is to be transmitted to the DAC, P3.3 is taken low.

Data on RxD is valid on the falling edge of TxD, so the clock

must be inverted as the DAC clocks data into the input shift

transmits its data in 8-bit bytes with only eight falling clock

edges occurring in the transmit cycle. As the DAC requires a

14-bit word, P3.3 (or any one of the other programmable bits)

is the

CS_DAC input signal to the DAC, so P3.3 should be

brought low at the beginning of the 16-bit write cycle 2

8-bit

words and held low until the 16-bit 2

8 cycle is completed.

After that, P3.3 is brought high again and the new data loads to

the DAC. Again, the first two bits, after rearranging, should be

DON’T CARE.

APPLICATIONS

Optocoupler Interface

The digital inputs of the DAC are Schmitt-triggered, so they

can accept slow transitions on the digital input lines. This makes

these parts ideal for industrial applications where it may be

necessary for the DAC to be isolated from the controller via

optocouplers. Figure 37 illustrates such an interface.

VDD

10k

VDD

10k

VDD

10k

DIN

SCLK

CS_DAC

DIN

GND

VDD

VOUT

DAC

POWER

0.1nF

10nF

REGULATOR

Figure 37. DAC in an Optocoupler Interface

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