AD15700SLASHPCB datasheet(36/44 Pages) AD

36 / 44 page

REV. A

–36–

AD15700

The AD15700’s ADC has five different ground pins: INGND,

REFGND, AGND, DGND, and OGND. INGND is used to

sense the analog input signal. REFGND senses the reference

voltage and should be a low impedance return to the reference

because it carries pulsed currents. AGND is the ground to which

most internal ADC analog signals are referenced. This ground

must be connected with the least resistance to the analog ground

plane. DGND must be tied to the analog or digital ground plane

depending on the configuration. OGND is connected to the

digital system ground.

The layout of the decoupling of the reference voltage is important.

The decoupling capacitor should be close to the ADC and connected

with short and large traces to minimize parasitic inductances.

100

VREF = 2.5V

VDD = 5V

TA = 25 C

2 s/DIV

VOUT = (50mV/DIV)

CLOCK (5V/DIV)

Figure 27. Digital Feedthrough

100

VREF = 2.5V

VDD = 5V

TA = 25 C

2 s/DIV

CS (5V/DIV)

VOUT (0.1V/DIV)

Figure 28. Digital-to-Analog Glitch Impulse

100

2 s/DIV

VREF = 2.5V

VDD = 5V

TA = 25 C

50pF

100pF

200pF

10pF

(5V/DIV)

VOUT

(0.5V/DIV)

Figure 29. Large Signal Settling Time

100

VOUT (1V/DIV)

VOUT (50mV/DIV)

GAIN = –216

VREF = 2.5V

VDD = 5V

TA = 25 C

0.5 s/DIV

Figure 30. Small Signal Settling Time

DAC Circuit Information

The DAC is a single 14-bit, serial input voltage output. It

operates from a single supply ranging from 2.7 V to 5 V and

consumes typically 300 mA with a supply of 5 V. Data is written

to the devices in a 14-bit word format, via a 3- or 4-wire serial

interface. To ensure a known power-up state, the parts were

designed with a power-on reset function. In unipolar mode, the

output is reset to 0 V.

Digital-to-Analog Section

The DAC architecture consists of two matched DAC sections.

A simplified circuit diagram is shown in Figure 31. The four

MSBs of the 14-bit data-word are decoded to drive 15 switches,

E1 to E15. Each of these switches connects one of 15 matched

resistors to either AGND or VREF. The remaining 10 bits of

the data-word drive switches S0 to S9 of a 10-bit voltage mode

R-2R ladder network.

E15

VOUT

10-BIT R-2R LADDER

FOUR MSBS DECODED INTO

15 EQUAL SEGMENTS

Figure 31. DAC Architecture

With this type of DAC configuration, the output impedance is

independent of code, while the input impedance seen by the

reference is heavily code dependent. The output voltage is

dependent on the reference voltage as shown in the following

equation.

OUT

REF

where D is the decimal data-word loaded to the DAC register

and N is the resolution of the DAC. For a reference of 2.5 V,

the equation simplifies to the following.

OUT

16 384

giving a VOUT of 1.25 V with midscale loaded, and 2.5 V with

full scale loaded to the DAC.

The LSB size is VREF/16,384.

AD15700/PCB Datasheet(PDF) 36 Page - Analog Devices

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