AD15700SLASHPCB datasheet(37/44 Pages) AD

37 / 44 page

REV. A

AD15700

–37–

Serial Interface

The DAC is controlled by a versatile 3-wire serial interface that

operates at clock rates up to 25 MHz and is compatible with

SPI, QSPI, MICROWIRE, and DSP interface standards. The

timing diagram can be seen in Figure 3. Input data is framed by

the chip select input,

CS_DAC. After a high to low transition on

CS_DAC, data is shifted synchronously and latched into the

input register on the rising edge of the serial clock, SCLK. Data

is loaded MSB first in 14-bit words. After 14 data bits have been

loaded into the serial input register, a low to high transition on

CS_DAC transfers the contents of the shift register to the DAC.

Data can only be loaded to the part while

CS_DAC is low.

Unipolar Output Operation

The DAC is capable of driving unbuffered loads of 60 k

Unbuffered operation results in low supply current, typically

300 mA, and a low offset error. The DAC provides a unipolar

output swing ranging from 0 V to VREF. Figure 32 shows a

typical unipolar output voltage circuit. The code table for this

mode of operation is shown in Table IV.

DAC

DGND

AGND

SCLK

DIN

VDD

VREF

SERIAL

INTERFACE

UNIPOLAR

OUTPUT

OP AMP

10 F

2.5V

0.1 F

OUT

Figure 32. Unipolar Output

Table IV. Unipolar Code Table

DAC Latch Contents

MSB

LSB

Analog Output

11 1111 1111 1111

VREF X (16383/16384)

10 0000 0000 0000

VREF X (8192/16384) = 1/2 VREF

00 0000 0000 0001

VREF X (1/16384)

00 0000 0000 0000

0 V

Assuming a perfect reference, the worst-case output voltage may

be calculated from the following equation.

INL

OUT UNI

REF

ZSE

–

=¥

()++

where:

VOUT –UNI = Unipolar Mode Worst-Case Output

D = Decimal Code Loaded to DAC

VREF = Reference Voltage Applied to Part

VGE = Gain Error in Volts

VZSE = Zero Scale Error in Volts

INL = Integral Nonlinearity in Volts

Output Amplifier Selection

In a single-supply application, selection of a suitable op amp

may be more difficult as the output swing of the amplifier does

not usually include the negative rail, in this case AGND. This

can result in some degradation of the specified performance

unless the application does not use codes near zero.

The selected op amp needs to have very low offset voltage (the

DAC LSB is 152

mV with a 2.5 V reference) to eliminate the

need for output offset trims. Input bias current should also be

very low as the bias current multiplied by the DAC output

impedance (approximately 6 k

W) will add to the zero code error.

Rail-to-rail input and output performance is required. For fast

settling, the slew rate of the op amp should not impede the

settling time of the DAC. Output impedance of the DAC is

constant and code independent, but in order to minimize gain

errors, the input impedance of the output amplifier should be as

high as possible. The amplifier should also have a 3 dB band-

width of 1 MHz or greater. The amplifier adds another time

constant to the system, thus increasing the settling time of the

output. A higher 3 dB amplifier bandwidth results in a faster

effective settling time of the combined DAC and amplifier.

Force Sense Buffer Amplifier Selection

These amplifiers can be single-supply or dual-supply, low noise

amplifiers. A low output impedance at high frequencies is pre-

ferred to be able to handle dynamic currents of up to

±20 mA.

Reference and Ground

As the input impedance is code dependent, the reference pin

should be driven from a low impedance source. The DAC oper-

ates with a voltage reference ranging from 2 V to VDD. Although

DAC’s full-scale output voltage is determined by the reference,

references below 2 V will result in reduced accuracy. Table IV

outlines the analog output voltage for particular digital codes.

Power-On Reset

The DAC has a power-on reset function to ensure the output is

at a known state upon power-up. On power-up, the DAC register

contains all zeros, until data is loaded from the serial register.

However, the serial register is not cleared on power-up, so its

contents are undefined. When loading data initially to the DAC,

14 bits or more should be loaded to prevent erroneous data

appearing on the output. If more than 14 bits are loaded, only the

last 14 are kept, and if fewer than 14 are loaded, bits will remain

from the previous word. If the DAC needs to be interfaced with

data shorter than 14 bits, the data should be padded with zeros

at the LSBs.

Power Supply and Reference Bypassing

For accurate high resolution performance, it is recommended

that the reference and supply pins be bypassed with a 10 nF

tantalum capacitor in parallel with a 0.1 nF ceramic capacitor.

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the DAC is via a serial bus that

uses standard protocol compatible with DSP processors and

microcontrollers. The communications channel requires a

3-wire interface consisting of a clock signal, a data signal, and a

synchronization signal. The DAC requires a 14-bit data-word

with data valid on the rising edge of SCLK. The DAC update

may be done automatically when all the data is clocked in.

AD15700/PCB Datasheet(PDF) 37 Page - Analog Devices

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