LM1269 datasheet(19/20 Pages) NSC

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DAC Interface Register Definitions

(Continued)

Bit 7

Bit 0

D3–7 D3–6 D3–5 D3–4 D3–3 D3–2 D3–1 D3–0

Bits 7–0: DAC 3. These eight bits determine the output

voltage of DAC 3.

DAC 4 Register (I

2C address 07h)

Bit 7

Bit 0

D4–7 D4–6 D4–5 D4–4 D4–3 D4–2 D4–1 D4–0

Bits 7–0: DAC 4. These eight bits determine the output

voltage of DAC 4.

DC Offset and OSD Contrast Control Register (I

2C ad-

dress 08h)

Bit 7

Bit 0

RSV

OSDC1

OSDC0

DC2

DC1

DC0

Bits 2–0: DC Offset Control. These three bits determine the

active video DC offset to all three channels.

Bits 4–3: OSD Contrast Control. These two bits determine

the contrast level of the OSD information.

Bits 7–5: Reserved.

Global Video Control Register (I

2C address 09h)

Bit 7

Bit 0

RSV

DCF4

DCF1–3

Bit 0:

Blank Video. When this bit is a one, blank the

video output. When this bit is a zero allow normal

video out.

Bit 1:

Power Save. When this bit is a one, shut down

the analog circuits to support sleep mode. When

this bit is a zero enable the analog circuits for

normal operation.

Bit 2:

MUST BE SET TO “0” FOR PROPER OPERA-

TION.

Bit 3:

DAC1–3 Configuration. When this bit is a zero

the DAC outputs of DAC1–3 are full scale

(0V–4.5V). When this bit is 1, the range of

DAC1–3 are halved (0V–2.25V).

Bit 4:

DAC4 Configuration. When this bit is a zero the

DAC4 output is not mixed with the other DAC

outputs. When the bit is one, 50% of the DAC4

output is added to DAC1–3.

Bit 5:

MUST BE SET TO “0” FOR PROPER OPERA-

TION.

Bits 7–6: Reserved.

Increment Mode Register (I

2C address 0Ah)

Bit 7

Bit 0

RSV

TST

INCR

Bit 0:

Increment Enable. When set to a “0”, the default

value, the increment mode is enabled. This al-

lows the registers to be updated sequentially by

sending another block of data.

Bit 1:

MUST BE SET TO “0” FOR PROPER OPERA-

TION.

Bits 7–2: Reserved.

Software Reset Register (I

2C address 0Fh)

Bit 7

Bit 0

RSV

SRST

Bit 0:

Software Reset. Setting this bit causes a software

reset. All registers (except this one) are loaded

with their default values. All operations currently

in progress are aborted (except for I

2C transac-

tions). This bit automatically clears itself when the

reset has been completed.

Bits 7–1: Reserved.

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