ADF4207 datasheet(9/20 Pages) AD

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CIRCUIT DESCRIPTION

REFERENCE INPUT SECTION

The reference input stage is shown in Figure 2. SW1 and SW2

are normally closed switches. SW3 is normally open. When

power-down is initiated, SW3 is closed and SW1 and SW2

are opened. Typical recommended external components are

shown in Figure 2.

30pF

OSCIN

OSC

OUT

TO R

COUNTER

BUFFER

POWER-DOWN

CONTROL

SW1

SW2

100k

SW3

18k

30pF

Figure 2. RF Input Stage

RF INPUT STAGE

The RF input stage is shown in Figure 3. It is followed by a

2-stage limiting ampliﬁer to generate the CML clock levels needed

for the prescaler.

RFINA

BIAS

GENERATOR

1.6V

AGND

RFINB

Figure 3. RF Input Stage

PRESCALER

The dual modulus prescaler (P/P + 1), along with the A and

B counters, enables the large division ratio, N, to be realized

(N = BP + A). This prescaler, operating at CML levels, takes

the clock from the RF input stage and divides it down to a man-

ageable frequency for the CMOS A and B counters. It is based

on a synchronous 4/5 core.

The prescaler is selectable. Both RF1 and RF2 can be set to

either 32/33 or 64/65. DB20 of the AB counter latch selects

the value. See Tables IV and VI.

A AND B COUNTERS

The A and B CMOS counters combine with the dual modulus

prescaler to allow a wide ranging division ratio in the PLL feed-

back counter. The devices are guaranteed to work when the

prescaler output is 200 MHz or less.

Pulse Swallow Function

The A and B counters, in conjunction with the dual modulus

prescaler, make it possible to generate output frequencies that

are spaced only by the Reference Frequency divided by R. The

equation for the VCO frequency is as follows:

fVCO = [(P

× B) + A] × fREFIN/R

fVCO = Output frequency of external voltage controlled

oscillator (VCO).

= Preset modulus of dual modulus prescaler

(32/33, 64/65).

= Preset Divide Ratio of binary 11-bit counter

(1 to 2047).

= Preset Divide Ratio of binary 6-bit A counter

(0 to 63).

fREFIN = Output frequency of the external reference frequency

oscillator.

= Preset divide ratio of binary 14-bit programmable

reference counter (1 to 16383).

R COUNTER

The 14-bit R counter allows the input reference frequency to

be divided down to produce the reference clock to the phase

frequency detector (PFD). Division ratios from 1 to 16,383

are allowed.

PRESCALER

P/P + 1

MODULUS

CONTROL

FROM RF

INPUT STAGE

LOAD

N = BP + A

N DIVIDER

LOAD

TO PFD

11-BIT B

COUNTER

6-BIT A

COUNTER

Figure 4. A and B Counters

PHASE FREQUENCY DETECTOR (PFD) AND CHARGE

PUMP

The PFD takes inputs from the R counter and N counter (N =

BP + A) and produces an output proportional to the phase and

frequency difference between them. Figure 5 is a simpliﬁed

schematic.

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