AS7C1024A

AS7C31024A

9/26/02; 0.9.9

Alliance Semiconductor

P. 6 of 9

®

AC test conditions

Notes

2

This parameter is sampled and not 100% tested.

3

For test conditions, see AC Test Conditions, Figures A, B, and C.

5

This parameter is guaranteed, but not 100% tested.

6WE is High for read cycle.

7CE1 and OE are Low and CE2 is High for read cycle.

8

Address valid prior to or coincident with CE1 transition Low.

9

All read cycle timings are referenced from the last valid address to the first transitioning address.

10 CE1 or WE must be High or CE2 Low during address transitions. Either CE1 or WE asserting high terminates a write cycle.

11 All write cycle timings are referenced from the last valid address to the first transitioning address.

12 CE1 and CE2 have identical timing.

13 C=30pF, except all high Z and low Z parameters, C=5pF.

14 2V data retention applies to commercial temperature operating range only.

255

Ω

– Output load: see Figure B or Figure C.

– Input pulse level: GND to 3.0V. See Figure A.

– Input rise and fall times: 2 ns. See Figure A.

– Input and output timing reference levels: 1.5V.

C(14)

320

Ω

GND

+3.3V

168

Ω

Thevenin equivalent:

+1.728V (5V and 3.3V)

Figure C: 3.3V Output load

255

Ω

C(14)

480

Ω

GND

+5V

Figure B: 5V Output load

10%

90%

10%

90%

GND

+3.0V

Figure A: Input pulse

2 ns