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TAS6424 Datasheet(PDF) 8 Page - Texas Instruments |
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TAS6424 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 68 page  8 TAS6424-Q1 SLOS870A – SEPTEMBER 2016 – REVISED OCTOBER 2016 www.ti.com Product Folder Links: TAS6424-Q1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Electrical Characteristics (continued) Test conditions (unless otherwise noted): TC = 25°C, PVDD = VBAT = 14.4 V, VDD = 3.3 V, RL = 4 Ω, Pout = 1 W/ch, ƒ = 1 kHz, fSW = 2.11 MHz, AES17 Filter, default I 2C settings, see Figure 79 and Figure 82 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AUDIO PERFORMANCE Vn Output noise voltage Zero input, A-weighting, gain level 1, PVDD = 14.4 V 42 μV Zero input, A-weighting, gain level 2, PVDD = 14.4 V 55 Zero input, A-weighting, gain level 3, PVDD = 18 V 67 Zero input, A-weighting, gain level 4, PVDD = 25 V 85 GAIN Peak output voltage/dBFS Gain level 1, Register 0x01, bit 1-0 = 00 7.5 V/FS Gain level 2, Register 0x01, bit 1-0 = 01 15 Gain level 3, Register 0x01, bit 1-0 = 10 21 Gain level 4, Register 0x01, bit 1-0 = 11 29 Crosstalk Channel crosstalk PVDD = 14.4 Vdc + 1 VRMS, ƒ = 1 kHz 90 dB PSRR Power-supply rejection ratio PVDD = 14.4 Vdc + 1 VRMS, ƒ = 1 kHz 75 dB THD+N Total harmonic distortion + noise 0.02% GCH Channel-to-channel gain variation –1 0 1 dB LINE OUTPUT PERFORMANCE Vn_LINEOUT LINE output noise voltage Zero input, A-weighting, channel set to LINE MODE 42 μV VO_LINEOUT LINE output voltage 0-dB input, channel set to LINE MODE 5.5 VRMS THD+N Line output total harmonic distortion + noise VO = 2 VRMS , channel set to LINE MODE 0.01% DIGITAL INPUT PINS VIH Input logic level high 70 %VDD VIL Input logic level low 30 %VDD IIH Input logic current, high VI = VDD 15 µA IIL Input logic current, low VI = 0 –15 µA PWM OUTPUT STAGE RDS(on) FET drain-to-source resistance Not including bond wire and package resistance 90 mΩ OVERVOLTAGE (OV) PROTECTION VPVDD_OV PVDD overvoltage shutdown 27.0 27.8 28.8 V VPVDD_OV_HY S PVDD overvoltage shutdown hysteresis 0.3 V VVBAT_OV VBAT overvoltage shutdown 19.3 20 V VVBAT_OV_HY S VBAT overvoltage shutdown hysteresis 0.3 V UNDERVOLTAGE (UV) PROTECTION VBATUV VBAT undervoltage shutdown 4 4.5 V VBATUV_HYS VBAT undervoltage shutdown hysteresis 0.2 V PVDDUV PVDD undervoltage shutdown 4 4.5 V PVDDUV_HY S PVDD undervoltage shutdown hysteresis 0.2 V BYPASS VOLTAGES VGVDD Gate drive bypass pin voltage 7 V VAVDD Analog bypass pin voltage 6 V VVCOM Common bypass pin voltage 2.5 V VVREG Regulator bypass pin voltage 5.5 V POWER-ON RESET (POR) VPOR VDD voltage for POR 2.1 2.7 V VPOR_HY VDD POR recovery hysteresis voltage 0.5 V OVERTEMPERATURE (OT) PROTECTION OTW(i) Channel overtemperature warning 150 °C OTSD(i) Channel overtemperature shutdown 175 °C OTW Global junction overtemperature warning Set by register 0x01 bit 5-6, default value 130 °C OTSD Global junction overtemperature shutdown 160 °C |
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