MT9072AB datasheet(54/275 Pages) ZARLINK

54 / 275 page

MT9072

Data Sheet

Zarlink Semiconductor Inc.

Figure 7 - Synchronization State Diagram (E1)

6.0

Elastic Buffer

The MT9072 has a two frame receive elastic (or slip) buffer, which absorbs wander and low frequency jitter in

multi-trunk applications. If desired, the elastic buffer can be bypassed by using the Data Link RxDL pin output (see

the following section). The received data (RPOS and RNEG) is clocked into the elastic buffer with the extracted

(EXCLi pin) clock and is clocked out of the elastic buffer with the system (CKi pin) clock. The EXCLi clock is

generated from the receive data, and is therefore phase-locked with that data. In normal operation, the EXCLi clock

400 msec timer expired

>914 CRC errors

in one second

3 consecutive incorrect

frame alignment

signals

YES

CRC-to-non-CRC interworking. Maintain

primary basic frame alignment. Continue

to send CRC-4 data, but stop CRC

processing. E-bits set to ‘0’. Indicate

CRC-to-non-CRC operation. Note 7.

Search for primary basic

frame alignment signal

RAI=1, Es=0.

Out of synchronization

Verify Bit 2 of non-frame

alignment signal.

Parallel search for new basic

frame alignment signal.

Notes 6 & 7.

YES

CRC multiframe

alignment

* only if CRC-4 synchronization is selected and

automatic CRC-4 interworking is de-selected.

** only if automatic CRC-4 interworking is selected.

8 msec. timer

expired**

CRC-to-CRC interworking. Re-align to new

basic frame alignment. Start CRC-4

processing. E-bits set as per G.704 and

I.431. Indicate CRC synchronization

achieved.

Notes 7 & 8.

signaling multi-frame

alignment

Primary basic frame

synchronization acquired. Enable

traffic RAI=0, E’s=0. Start loss of

primary basic frame alignment

checking. Notes 7 & 8.

YES

CRC-4 multi-frame

alignment

YES

Verify second

occurrence of frame

alignment signal.

Start 8 msec timer.

Note 7.

Multiframe synchronization

acquired as per G.732.

Note 7.

Find two CRC frame

alignment signals.

Note 7.

Check for two consecutive errored

multiframe alignment signals.

Notes 7 & 8.

Start 400 msec timer.

Note 7.

Search for multiframe

alignment signal.

Note 7.

YES

Basic frame

alignment acquired

No CRC

multiframe

alignment.

No CRC multiframe

alignment.

8 msec. timer

expired*

RAI = 0

MT9072AB Datasheet(PDF) 54 Page - Zarlink Semiconductor Inc

MT9072AB Datasheet(HTML) 54 Page - Zarlink Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL