MT9072AB datasheet(93/275 Pages) ZARLINK

93 / 275 page

MT9072

Data Sheet

Zarlink Semiconductor Inc.

14.2

E1 Maintenance and Alarms

Extensive maintenance and alarm generation and detection functions are provided on the MT9072. The following

table groups the registers for control and monitor of these functions.

14.2.1

E1 Error Insertion

Six types of error conditions can be inserted into the transmit PCM30 data stream through register control bits

located at address Y01. These error events include the bipolar violation errors (BVE), CRC-4 errors (CRCE), FAS

errors (FASE), NFAS errors (NFSE), payload (PERR) and a loss of signal error (LOSE). The LOSE function

overrides the HDB3 encoding function (no BPV are added). Also included are E1 and E2 error bit insertion on

frames 13 and 15. See the bit descriptions (control register address Y01) for additional details.

14.2.2

E1 Per Timeslot Control

There are 32 per timeslot control registers occupying a total of 32 unique addresses (Y90-YAF). Each register

controls a matching timeslot on the 32 transmit channels (onto the line) and the equivalent channel data on the

receive (DSTo) data. For example, register address Y91 of the first per timeslot control register contains program

control for transmit timeslot 1 and DSTo channel 1.

14.2.3

E1 Per Timeslot Looping

Any channel or combination of channels may be looped from transmit (sourced from DSTi) to receive (output on

DSTo) ST-BUS channels. When bit 4 (LTSL) in the Per Timeslot Control Word is set the data from the equivalent

transmit timeslot is looped back onto the equivalent receive channel.

Any channel or combination of channels may be looped from receive (sourced from the line data) to transmit

(output onto the line) channels. When bit 5 (RTSL) in the Per Timeslot Control Word is set the data from the

equivalent receive timeslot is looped back onto the equivalent transmit channel.

Address

Description

Y00

Alarm and Framing Control Register The TAIS and E bit errors and RAI can be set by this register.

Y01

Test Error and Loopback Control

BPVE, CRCE,FASE, NFSE and E bit errors can be inserted.

Y05

CAS Control and Data Register

The Y bit can be used to send Remote Multiframe Alarm signal.

Y10

Synchronization and CRC-4

Remote Status

The bits of this register provide good receiver error status.

Y11

CRC-4 Timer and CRC-4 Local

Status

The CRC-4 errors are registered in Y11.

Y12

Alarms and MAS Status

This register provides AIS, RAI, LOSS status bits.

Y24

Sync, CRC-4 remote alarm, MAS

Latched Status Register

Latched version of receive CRC errors and synchronization loss

are available.

Y34

Sync, CRC-4 Remote Alarm, MAS

Interrupt status register

This register provides bits for interrupt generation for Y24 CRC

errors and synchronization loss functions.

Y44

Sync, CRC-4 Remote Alarm, MAS

Interrupt register mask

This register provides bits for interrupt mask register for Y34.

Table 47 - Registers Related to Maintenance and Alarms (E1)

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