MT9072AB datasheet(58/275 Pages) ZARLINK

58 / 275 page

MT9072

Data Sheet

Zarlink Semiconductor Inc.

7.1.1

T1 Data Link (DL) Pin Access

When EDLEN(Y06) is set to "1" the data link (DL) bits can be sourced/sinked to and from the TxDL and RxDL pins,

by enabling the corresponding pulses in either gapped clocks or enable low signals provided at the RxDLC and

TxDLC pins. The option of either gapped clock or enable signal is selected by control bit DLCK (Register address

Y06).

In D4 or ESF mode, the optional serial data link operates at 4 khz. In D4 mode the data link pins are used to

send/receive Fs bits only, while the Ft bits are generated internally. See Figures 40 to 43.

7.1.1.1

T1 Data Link (DL) Pin Data Received from PCM24

The RxDLC clock is derived from the receive extracted clock (EXCLi).The B8ZS decoded receive data, at

1.544 Mbit/s, is clocked out of the device on the RxDL pin with the rising edge of EXCLi and is aligned to RXDLC. In

order to facilitate the attachment of this data stream to a Data Link controller, the clock signal RxDLC (falling edge

of EXCLi) consists of positive pulses, of nominal width of 344 ns, during the Fs bit cell times that are selected for the

Data Link, with the rising edge aligned with the middle of the bit cell. DL data will not be lost or repeated when a

receive frame slip occurs as the DL data does not pass through the elastic buffer. See Figures 42 to 43 for timing

requirements.

7.1.1.2

T1 Data Link (DL) Pin Data Sent to PCM24

The TxDLC clock is derived from the transmit clock (TXCL) and is provided one frame before its usage on the

appropriate S-bit. Hence the TXDLC clock is provided one frame before it is used in ESF Mode in Frames 2, 4, 6, 8,

10, 12, 14, 16, 18, 20, 22, 24. See Figures 40 to 41 for timing requirements.

Address

Description

Y06

HDLC and Data Link Control

This register determines the source of the Data Link which can be

the HDLC, Bit Oriented messages or the external Data Link. This

Data Link interface.

Y07

Transmit bit Oriented Message This register holds the message that will be sent in ESF FDL if the

BOMEN bit in Y06 is set.

Y08

Receive bit Oriented Message

Match

This register is the match register for received bit oriented message

Y12

Receive bit Oriented Message This register holds the value of the receive bit oriented message

Y25

Receive Line Status and Timer

Latch

This register contains bit oriented message and bit oriented

message match latch bits.

Y35

Receive Line and Timer

Interrupt Status

This register contains bit oriented message and bit oriented

message match interrupt status bits.

Y45

Receive Line and Timer

Interrupt Mask

These are the mask bits for Y35.

Table 16 - Registers Related to the Data Link and Bit Oriented Messages (T1)

MT9072AB Datasheet(PDF) 58 Page - Zarlink Semiconductor Inc

MT9072AB Datasheet(HTML) 58 Page - Zarlink Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL