MT9072AB datasheet(139/275 Pages) ZARLINK

139 / 275 page

MT9072

Data Sheet

139

Zarlink Semiconductor Inc.

Bit

Name

Functional Description

15-9

not used.

8GAIM

(0)

Go Ahead Interrupt Mask. When unmasked an interrupt is generated when go-ahead

pattern (01111111) was detected by the HDLC receiver.

7EOPDIM

(0)

End of Packet Data Interrupt Mask. When unmasked an interrupt is initiated when an end

of packet (EOP) byte was written into the RX FIFO by the HDLC receiver.

TEOPIM

(0)

Transmit End of Packet Interrupt Mask. When unmasked an interrupt is initiated when

the transmitter has finished sending the closing flag of a packet or after a packet has been

aborted.

5EOPRIM

(0)

End of Packet Received Interrupt Mask. When unmasked an interrupt is initiated when

the byte about to be read from the RX FIFO is the last byte of the packet. An interrupt is

also initiated if the Rx FIFO is read and there is no data in it.

4TXFLIM

(0)

Transmit Fifo Low Interrupt Mask. When unmasked an interrupt is initiated when the Tx

FIFO is emptied below the selected low threshold level.

3FAIM

(0)

Frame Abort: Transmit Interrupt Mask. When unmasked an interrupt is initiated this bit

(FA) is set when a frame abort is received during packet reception. It must be received after

a minimum number of bits have been received (26) otherwise it is ignored.

TXUNDERIM

(0)

Transmit Fifo Underrun Interrupt Mask. When unmasked an interrupt is initiated for TX

FIFO underrun indication.

1RXFFIM

(0)

Receive Fifo full Threshold interrupt Mask. When unmasked an interrupt is initiated

whenever the Rx FIFO is filled above the 16 byte threshold level.

0RXOVFLIM

(0)

Receive Fifo Overflow Interrupt Mask. When unmasked an interrupt is initiated

whenever the 32 byte RX FIFO overflowed (i.e., an attempt to write to a 32 byte full RX

FIFO).

Table 105 - HDLC Interrupt Mask Register(Y43) (T1)

Bit

Name

Functional Description

FEOIM

(0)

Framing Bit Error Counter Overflow Interrupt Mask. When unmasked an interrupt is

initiated whenever the framing bit error counter changes from FFH to 00H. 1 -masked, 0 -

unmasked.

CRCOIM

(0)

CRC-6 Error Counter Overflow Interrupt Mask. When unmasked an interrupt is initiated

whenever the CRC-6 error counter changes from FFH to 00H. 1 - masked, 0 - unmasked.

OOFOIM

(0)

Out Of Frame Counter Overflow Interrupt Mask. When unmasked an interrupt is

initiated whenever the out of frame counter changes state from changes from FFH to 00H.

1 - masked, 0 - unmasked.

COFAOIM

(0)

Change of Frame Alignment Counter Overflow Interrupt Mask. When unmasked an

interrupt is initiated whenever the change of frame alignment counter changes from FFH to

00H. 1 - masked, 0 - unmasked.

Table 106 - Receive and Sync Interrupt Mask Register(Y44) (T1)

MT9072AB Datasheet(PDF) 139 Page - Zarlink Semiconductor Inc

MT9072AB Datasheet(HTML) 139 Page - Zarlink Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL