MT9072AB datasheet(158/275 Pages) ZARLINK

158 / 275 page

MT9072

Data Sheet

158

Zarlink Semiconductor Inc.

17.2

E1 Register Set

17.2.1

17.2.1.1

Framer Address (000-FFF) Summary

Binary Address

(A11-A0)

Hex

Address

Framer Accessed

0000 xxxx xxxx

0XX

0001 xxxx xxxx

1XX

0010 xxxx xxxx

2XX

0011 xxxx xxxx

3XX

0100 xxxx xxxx

4XX

0101 xxxx xxxx

5XX

0110 xxxx xxxx

6XX

0111 xxxx xxxx

7XX

1000 xxxx xxxx

1001 xxxx xxxx

8XX

900

901

902

903

904

905

910

911

912

913

920-93F

0 - 7, this performs an all framer write to register XX, except for the

following addresses which are common to all 8 framers:

Global Control 0(R/W)

Global Control 1(R/W)

Interrupt Vector 1 Mask Register (R/W)

Interrupt Vector 2 Mask Register (R/W)

Framer Loopback Register (R/W)

ST-BUS Analyser Interrupt Mask Register

Interrupt Vector1 Status Register(R)

Interrupt Vector2 Status Register(R)

ID Register (R)

ST-BUS Analyser Interrupt Status Register

ST-BUS Analyser Data

1010 0100 0000 -

1111 1111 1111

940 - FFF

not used

xxxx indicates all

(0000 to 1111) binary

possibilities

X indicates all (0 to

F) hex possibilities

Table 129 - Framer Addressing (000 - FFF) (E1)

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