MT9072AB datasheet(168/275 Pages) ZARLINK

168 / 275 page

MT9072

Data Sheet

168

Zarlink Semiconductor Inc.

17.2.2.8

Timeslot 0-31 Control Registers Address (Y90-YAF) Summary

yyyy 1000 0001 Y81

Channel 16 Receive CAS Data A16, B16, C16, D16

yyyy 1000 0010 Y82

Channel 17 Receive CAS Data A17, B17, C17, D17

yyyy 1000 0011 Y83

Channel 18 Receive CAS Data A18, B18, C18, D18

yyyy 1000 0100 Y84

Channel 19 Receive CAS Data A19, B19, C19, D19

yyyy 1000 0101 Y85

Channel 20 Receive CAS Data A20, B20, C20, D20

yyyy 1000 0110 Y86

Channel 21 Receive CAS Data A21, B21, C21, D21

yyyy 1000 0111 Y87

Channel 22 Receive CAS Data A22, B22, C22, D22

yyyy 1000 1000 Y88

Channel 23 Receive CAS Data A23, B23, C23, D23

yyyy 1000 1001 Y89

Channel 24 Receive CAS Data A24, B24, C24, D24

yyyy 1000 1010 Y8A

Channel 25 Receive CAS Data A25, B25, C25, D25

yyyy 1000 1011 Y8B

Channel 26 Receive CAS Data A26, B26, C26, D26

yyyy 1000 1100 Y8C

Channel 27 Receive CAS Data A27, B27, C27, D27

yyyy 1000 1101 Y8D

Channel 28 Receive CAS Data A28, B28, C28, D28

yyyy 1000 1110 Y8E

Channel 29 Receive CAS Data A29, B29, C29, D29

yyyy 1000 1111 Y8F

Channel 30 Receive CAS Data A30, B30, C30, D30

upper data bits (B15-4) are not used and may be any value if read

see the Register Group Address Summary for an explanation of yyyy and Y

Binary Address

(A10-A0)

Hex

Address

Control Bits

(Upper byte B15 - B8 unused, B8 - B0 are shown)

yyyy 1001 0000

Y90

Timeslot 0 Control

Set to 0

yyyy 1001 0001

Y91

Timeslot 1 Control

RADI1,MPDR1,MPDR1,CASS1, TADI1, RTSL1, LTSL1,

TTST1, RRST1, MPDT1, #

yyyy 1001 0010

Y92

Timeslot 2 Control

RADI2,MPDR2,MPDR2,CASS2, TADI2, RTSL2, LTSL2,

TTST2, RRST2, MPDT2, #

yyyy 1001 0011

Y93

Timeslot 3 Control

RADI3,MPDR3,MPDR3,CASS3,T ADI3, RTSL3, LTSL3,

TTST3, RRST3, MPDT3, #

yyyy 1001 0100

Y94

Timeslot 4 Control

RADI4,MPDR4,MPDR4,CASS4, TADI4, RTSL4, LTSL4,

TTST4, RRST4, MPDT4, #

yyyy 1001 0101

Y95

Timeslot 5 Control

RADI5,MPDR5,MPDR5,CASS5, TADI5, RTSL5, LTSL5,

TTST5, RRST5, MPDT5, #

Table 139 - Timeslot 0-31 Control Register (R/W) Address (Y9X, YAX) Summary (E1)

Binary Address

(A10-A0)

Hex

Address

Data Bits

(Upper bits B15 - B4 unused, B3 - B0 are shown)

Table 138 - Receive CAS Data Register (R) Address (Y7X,Y8X) Summary (E1)

MT9072AB Datasheet(PDF) 168 Page - Zarlink Semiconductor Inc

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