Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

MT9072AB Datasheet(PDF) 188 Page - Zarlink Semiconductor Inc

Part # MT9072AB
Description  Octal T1/E1/J1 Framer
PDF  275 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  ZARLINK [Zarlink Semiconductor Inc]
Direct Link  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

MT9072AB Datasheet(HTML) 188 Page - Zarlink Semiconductor Inc

Back Button MT9072AB Datasheet HTML 184Page - Zarlink Semiconductor Inc MT9072AB Datasheet HTML 185Page - Zarlink Semiconductor Inc MT9072AB Datasheet HTML 186Page - Zarlink Semiconductor Inc MT9072AB Datasheet HTML 187Page - Zarlink Semiconductor Inc MT9072AB Datasheet HTML 188Page - Zarlink Semiconductor Inc MT9072AB Datasheet HTML 189Page - Zarlink Semiconductor Inc MT9072AB Datasheet HTML 190Page - Zarlink Semiconductor Inc MT9072AB Datasheet HTML 191Page - Zarlink Semiconductor Inc MT9072AB Datasheet HTML 192Page - Zarlink Semiconductor Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 188 / 275 page
background image
MT9072
Data Sheet
188
Zarlink Semiconductor Inc.
Bit
Name
Functional Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SLC15
SLC14
SLC13
SLC12
SLC11
SLC10
SLC9
SLC8
SLC7
SLC6
SLC5
SLC4
SLC3
SLC2
SLC1
SLC0
Loss of Basic Frame Synchronization Counter. These bits make up a counter which is
incremented for each 125 us period in which basic frame synchronization (BSYNC=1
status register address Y10) is lost. This counter is cleared by a basic frame
synchronization to a loss of basic frame synchronization state transition (BSYNC=0 to 1),
or with an overflow, a RESET (RESET pin or RST bit), or it may be set by writing the
desired value to it. SLC0 is the least significant bit (LSB).
Table 159 - Loss of Basic Frame Synchronization Counter with Auto Clear (R/W Address Y16) (E1)
Bit
Name
Functional Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
EEC15
EEC14
EEC13
EEC12
EEC11
EEC10
EEC9
EEC8
EEC7
EEC6
EEC5
EEC4
EEC3
EEC2
EEC1
EEC0
E-bit Error Counter. These bits make up a counter which is incremented for each
received PCM30 CRC-4 submultiframe E-bit error. This counter is cleared with an
overflow, a RESET (RESET pin or RST bit), or may be set by writing the desired value to
it. EEC0 is the least significant bit (LSB).
Table 160 - E-bit Error Counter (R/W Address Y17) (E1)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com