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MT9072AB Datasheet(PDF) 232 Page - Zarlink Semiconductor Inc |
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MT9072AB Datasheet(HTML) 232 Page - Zarlink Semiconductor Inc |
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232 / 275 page  MT9072 Data Sheet 232 Zarlink Semiconductor Inc. Figure 18 - 8 E1 Links with Synchronous Common Channel Signaling for up to 24 Channels RPOS RNEG E2i TPOS TNEG T2o DSTo CSTo DSTi CSTi CKi FPi Framer 1/8 RPOS RNEG RCLK TPOS TNEG TCLK LIU 1/8 RT RR TT TR Transmit xfmr LINE 1 RCLK, TCLK RSP TSP F0 C2 Receive xfmr RCLK RDATA RSP SCLK TCLK TDATA TSP HDLC PRI SEC F0o C2o C4o C16o RCLK RSP TSP PLL From RCLK’s of LIU’s Notes: Framer 1-8, 1 of MT9072 LIU 1-8, of Generic LIU PLL, 1 of MT9044 HDLC, 1 of PEB 20320 (MUNICH 32) - Framer elastic buffer is used. - LIU Transmit JA and PLL are bypassed. RPOS RNEG E2i TPOS TNEG T2o DSTo CSTo DSTi CSTi CKi FPi Framer 8/8 RPOS RNEG RCLK TPOS TNEG TCLK LIU 8/8 RT RR TT TR Transmit xfmr LINE 8 Receive xfmr LINES 2 to 7 HDLC Timing Framers 2 to 7 DSTo CSTo DSTi CSTi CKi FPi LIU’s 2 to 7 6 6 1 1 |
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