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MT9072AB Datasheet(PDF) 268 Page - Zarlink Semiconductor Inc

Part # MT9072AB
Description  Octal T1/E1/J1 Framer
PDF  275 Pages
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Manufacturer  ZARLINK [Zarlink Semiconductor Inc]
Direct Link  http://www.zarlink.com
Logo ZARLINK - Zarlink Semiconductor Inc

MT9072AB Datasheet(HTML) 268 Page - Zarlink Semiconductor Inc

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MT9072
Data Sheet
268
Zarlink Semiconductor Inc.
Figure 69 - Receive Data Link Pin Functional Timing
RxBF
(Output)
Timeslot 0
Bit
1
Bit
0
Bit
7
Bit
6
Bit
5
Bit
2
Bit
4
Bit
3
Bit
7
Bit
6
Bit
5
Bit
4
Bit
1
Bit
0
Bit
7
Bit
6
Bit
5
Bit
2
Bit
4
Bit
3
Timeslot 31
Timeslot 1
Bit
Sa7
Bit
Sa8
Bit
Sa6
Bit
Sa4
Bit
Sa5
Bit
7
Bit
6
Bit
5
Bit
7
Bit
6
Bit
5
Bit
4
Bit
1
Bit
0
Bit
7
Bit
6
Bit
5
Bit
2
Bit
4
Bit
3
Example A - 20 kbit/s clock output
Example B - 12 kbit/s clock output
Sa4 to Sa8 clocked in by External Device
Sa4, Sa7 and Sa8 clocked in by External Device
RxDLC - Note 2
(Output)
RxDLC - Note 2
(Output)
RxDL
(Output)
E2i
RXDL
PCM 30
Bit Cells
Example B - enable output
Sa4, Sa7 and Sa8 clocked in by External Device
RxDLC - Note 3
(Output)
RxDLC - Note 3
(Output)
Example A - enable output
Sa4 to Sa8 clocked in by External Device
Note 1 - RxDLC output applies for every second frame (RxBF) pulse (250 us) only
Note 2 - Clock output provided by setting control bit DLCK=1 (register address Y08)
Note 3 - Enable output provided by clearing control bit DLCK=0 (register address Y08)
Note 4 - PCM Timeslot is with reference to RXDL Output. It is delayed 4 bits from RPOS/RNEG



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