SI3012 datasheet(39/54 Pages) ETC

39 / 54 page

Si3035

Rev. 1.2

Reset settings = 0000_0000 (serial mode 0, 1)

Reset settings = 0001_0011 (serial mode 2)

Reset settings = 0000_0000 (serial mode 0, 1, 2)

Reset settings = 0000_0000

Bit

D7D6D5

D4D3D2D1D0

Name

M1[7:0]

Type

R/W

Bit

Name

Function

7:0

M1[7:0]

M1 Multiplier.

Contains the (value – 1) for determining the output frequency on PLL1

Bit

D7D6D5

D4D3D2D1D0

Name

N2[3:0]

M2[3:0]

Type

R/W

Bit

Name

Function

7:4

N2[3:0]

N2 Divider.

Contains the (value – 1) for determining the output frequency on PLL2.

3:0

M2[3:0]

M2 Multiplier.

Contains the (value – 1) for determining the output frequency on PLL2.

Bit

D7D6D5

D4D3D2D1D0

Name

CGM

Type

R/W

Bit

Name

Function

7:1

Reserved

Read returns zero.

0CGM

Clock Generation Mode.

0 = No additional ratio is applied to the PLL and faster lock times are possible.

1 = A 25/16 ratio is applied to the PLL allowing for a more flexible choice of MCLK frequencies

while slowing down the PLL lock time.

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