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SI3012 Datasheet(PDF) 9 Page - List of Unclassifed Manufacturers

Part # SI3012
Description  3.3 V FCC/JATE DIRECT ACCESS ARRANGEMENT
PDF  54 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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SI3012 Datasheet(HTML) 9 Page - List of Unclassifed Manufacturers

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Si3035
Rev. 1.2
9
Figure 4. Serial Interface Timing Diagram (DCE = 1, FSD = 0)
Table 9. Switching Characteristics—Serial Interface (DCE = 1, FSD = 0)
(VA = Charge Pump, VD = 3.0 to 5.25 V, TA = 0 to 70°C for K-Grade, CL = 20 pF)
Parameter1,2
Symbol
Min
Typ
Max
Unit
Cycle Time, SCLK
tc
354
1/256 Fs
—
ns
SCLK Duty Cycle
tdty
—50
—
%
Delay Time, SCLK
↑ to FSYNC ↑
td1
—
—
10
ns
Delay Time, SCLK
↑ to FSYNC ↓
td2
—
—
10
ns
Delay Time, SCLK
↑ to SDO valid
td3
0.25tc – 20
—
0.25tc + 20
ns
Delay Time, SCLK
↑ to SDO Hi-Z
td4
—
—
20
ns
Delay Time, SCLK
↑ to RGDT ↓
td5
—
—
20
ns
Delay Time, SCLK
↑ to RGDT ↑
td6
—
—
20
ns
Setup Time, SDO Before SCLK
↓
tsu
25
—
—
ns
Hold Time, SDO After SCLK
↓
th
20
—
—
ns
Setup Time, SDI Before SCLK
tsu2
25
—
—
ns
Hold Time, SDI After SCLK
th2
20
—
—
ns
Notes:
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4 V, VIL = 0.4 V.
2. Refer to the section "Multiple Device Support" on page 25 for functional details.
SCLK
FSYNC
(m ode 1)
t
c
t
d1
t
d2
t
d2
FSYNC
(m ode 0)
t
d5
t
d6
t
d5
SDO
(m aster)
FSD
(M ode 0)
SDO
(slave 1)
t
d3
D15
D14
D13
D0
t
su
t
h
t
d4
t
d3
D15
t
d5
SDI
D15
D0
D1 4
t
h2
t
su2
t
d2
FSD
(M ode 1)
32 S C LK s
16 S C LK s
16 S C LK s
D13



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