V

T

Symbol

Parameter

Conditions

Min

Typ

Max

Units

V

OUTEN_IH

OUTEN Pin Input Logic

Low to Logic High Trip

Point

OUTEN Voltage

↑

3.5

3.0

V

V

OUTEN_IL

OUTEN Pin Input Logic

High to Logic Low Trip

Point

OUTEN Voltage

↓

1.8

1.5

V

V

REF

Band Gap Reference

I

1.225

1.256

1.287

V

V

REF_LOAD

Reference Voltage at

Full Load

I

1.223

1.254

1.285

V

V

REF_525

Reference Voltage at

High Line

I

1.226

1.257

1.288

V

V

REF_475

Reference Voltage at

Low Line

I

1.224

1.255

1.286

V

∆V

REF_LOAD

Reference Voltage

Load Regulation

I

−2

mV

∆V

REF_LINE

Reference Voltage Line

Regulation

I

5.25V to 4.75V

−0.5

mV

V

SAWL

Ramp Signal Valley

Voltage

1.25

V

V

SAWH

Ramp Signal Peak

Voltage

3.25

V

V

PWRBAD_GD

PWRGD Pin

Points (see Pin

Description for Pin 13)

% above DAC Output Voltage, when

Output Voltage

↑

10

%

% below DAC Output Voltage, when

Output Voltage

↓

−10

V

PWRGD_BAD

PWRGD Pin

Points (see Pin

Description for Pin 13)

% above DAC Output Voltage, when

Output Voltage

↓

8

%

% below DAC Output Voltage, when

Output Voltage

↑

−8

V

OVP

Over-voltage Protection

Trip Point

% above DAC Output Voltage

15

%

t

PWRGD

Power Good Response

Time

V

V

OUT

2

6

15

µs

t

PWRBAD

Power Not Good

Response Time

V

2

6

15

µs

I

OUTEN

OUTEN Pin Internal

Pull-Up Current

60

90

130

µA

V

VID_IH

VID Pins Logic High

Trip Point

3.5

3.0

V

V

VID_IL

VID Pins Logic Low

Trip Point

1.8

1.3

V

I

VID

VID0:4 Internal Pull-Up

Current

60

90

130

µA

t

SS

Soft Start Duration

2048

clock

cycles

Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Recommended Operating Conditions are conditions under which

the device operates correctly. Recommended Operating Conditions do not imply guaranteed performance limits.

The junction-to-ambient thermal resistance,

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