PCM1803DB datasheet(18/20 Pages) TI

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VINL, VINR Pins

VREF1 Pin

VREF2 Pin

DOUT Pin

System Clock

PCM1803

SLES125 – NOVEMBER 2004

APPLICATION INFORMATION (continued)

The VINL and VINR pins need a simple external RC filter (fC = 160 kHz) as an antialiasing filter to remove

out-of-band noise from the audio band. If the input signal includes noise with a frequency near the oversampling

frequency (64 fS or 128 fS), the noise is folded into the baseband (audio band) signal through A-to-D conversion.

The recommended R value is 100

Ω. Film-type capacitors of 0.01-µF should be located as close as possible to

the VINL and VINR pins and should be terminated to GND as close as possible to the AGND pin to maximize the

dynamic performance of ADC, by suppressing kickback noise from the PCM1803.

A 0.1-

µF ceramic capacitor and 10-µF electrolytic capacitor are recommended between V

REF1 and AGND to

ensure low source impedance of the ADC references. These capacitors should be located as close as possible

to the VREF1 pin to reduce dynamic errors on the ADC reference.

The differential voltage between VREF2 and AGND sets the analog input full-scale range. A 0.1-µF ceramic

capacitor and 10-

µF electrolytic capacitor are recommended between V

REF2 and AGND. These capacitors should

be located as close as possible to the VREF2 pin to reduce dynamic errors on the ADC reference.

The DOUT pin has enough load drive capability, but if the DOUT line is long, locating a buffer near the PCM1803

and minimizing load capacitance is recommended to minimize the digital-analog crosstalk and maximize the

dynamic performance of the ADC.

The quality of the system clock can influence the dynamic performance, because the PCM1803 operates based

on a system clock. Therefore, it may be required to consider the system-clock duty, jitter, and the time difference

between system-clock transition and BCK or LRCK transition in the slave mode.

PCM1803DB Datasheet(PDF) 18 Page - Texas Instruments