SDA9401 datasheet(4/69 Pages) ETC

4 / 69 page

SDA 9401

Micronas

Preliminary Data Sheet

General description

The SDA 9401 is a new component of the Micronas MEGAVISION® IC set in a 0.35 µm embedded

DRAM technology (field memory embedded). The SDA 9401 is pin compatible to the SDA 9400

(frame memory embedded). The SDA 9401 comprises all main functionalities of a digital featurebox

in one monolithic IC.

The SDA 9401 does a simple 100/120 Hz interlaced (50/60 Hz progressive) scan rate conversion.

The scan rate converted picture can be vertically expanded. The SDA 9401 has a freerunning

mode, therefore features like multiple picture display (e.g. tuner scan) are possible.

The noise reduction is field based. Furthermore separate motion detectors for luminance and

chrominance have been implemented. For automatic controlling of the noise reduction parameters a

noise measurement algorithm is included, which measures the noise level in the picture or in the

blanking period. In addition a spatial noise reduction is implemented, which reduces the noise even

in the case of motion. The input signal can be compressed horizontally and vertically with a certain

number of factors. Therefore split screen modes are supported too.

Beside these additional functions like coloured background, windowing and flashing are

implemented.

Features

• Two input data formats

- 4:2:2 luminance and chrominance parallel (2 x 8 wires)

- ITU-R 656 data format (8 wires)

• Two different representations of input chrominance data

- 2‘s complement code

- Positive dual code

• Flexible input sync controller

• Flexible compression of the input signal

- Digital vertical compression of the input signal (1.0, 1.25, 1.5, 1.75, 2.0, 3.0, 4.0)

- Digital horizontal compression of the input signal (1.0, 2.0, 4.0)

• Noise reduction

- Motion adaptive spatial and temporal noise reduction (3D-NR)

- Temporal noise reduction for luminance field based

- Temporal noise reduction for chrominance field based

- Separate motion detectors for luminance and chrominance

- Flexible programming of the temporal noise reduction parameters

- Automatic measurement of the noise level (5 bit value, readable by I²C bus)

• TV mode detection by counting line numbers (PAL, NTSC, readable by I²C bus)

• Embedded memory

- 3.2 Mbit embedded DRAM core for field memories

- 128 kbit embedded DRAM core for line memories

SDA9401 Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers