SDA9401 datasheet(8/69 Pages) ETC

8 / 69 page

SDA 9401

Micronas

Preliminary Data Sheet

Pin description

S: supply,

I: input,

O: output,

TTL: digital (TTL)

ANA: analog

PD: pull down

Pin No.

Name

Type

Description

2,8,24,42,55

VSS1

Supply voltage ( VSS = 0 V )

9,25,41,56

VDD1

Supply voltage ( VDD = 3.3 V )

36,52,58

VSS2

Supply voltage ( VSS = 0 V )

35,51,53,57,

VDD2

Supply voltage ( VDD = 3.3 V )

43,..,50

YIN0...7

I/TTL

Data input Y (see input data format)

31,..,34;37,...,

UVIN0...7

I/TTL

Data input UV (for 4:2:2 parallel, see input data format)

(for CCIR 656, see input data format)

RESET

I/TTL

System reset. The RESET input is low active. In order to

ensure correct operation a "Power On Reset" must be

performed. The RESET pulse must have a minimum

duration of two clock periods of the system clock CLK1.

HIN

I/TTL

H-Sync input

(only for full CCIR 656)

VIN

I/TTL

V-Sync input

(only for full CCIR 656)

SYNCEN

I/TTL

Synchronization enable input

SDA

I/O

I2C-Bus data line (5V ability)

SCL

I2C-Bus clock line (5V ability)

CLK1

I/TTL

System clock 1

17,..,10

UVOUT0...7

O/TTL Data output UV (see output data format)

7,..,3;1;64;63 YOUT0...7

O/TTL Data output Y (see output data format)

HREF

O/TTL Horizontal active video output

VOUT

I/TTL

V-Sync output

HOUT

I/TTL

H-Sync output

INTERLACED O/TTL Interlace signal for AC coupled vertical deflection

X1 / CLK2

I/TTL

Crystal connection / System clock 2

O/ANA Crystal connection

CLKOUT

O/TTL Clock output (depends on I²C parameters CLK11EN,

CLK21EN, see also

Clock concept on page 27)

TEST

I/TTL

Test input, connect to VSS for normal operation

SDA9401 Datasheet(PDF) 8 Page - List of Unclassifed Manufacturers

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