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SDA9401 Datasheet(PDF) 13 Page - List of Unclassifed Manufacturers

Part # SDA9401
Description  Scan Rate Converter using Embedded DRAM Technology Units
PDF  69 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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Preliminary Data Sheet
SDA 9401
Input data formats
Xab: X: signal component a: sample number b: bit number
Input sync formats
The amplitude resolution for each input signal component is 8 bit, the maximum clock frequency is
27 MHz. Consequently the SDA 9401 is dedicated for application in high quality digital video
systems.
The figure below shows the generation of the internal H- and V-syncs in case of full CCIR 656
mode. The H656 sync is generated after the EAV. The V656 and F656 signals change
synchronously with the EAV timing reference code.
Data
Pin
CCIR 656
FORMAT = 1X
FORMAT = 01
4:2:2 Parallel
FORMAT = 00
YIN7
U07
Y07
V07
Y17
Y07
Y17
YIN6
U06
Y06
V06
Y16
Y06
Y16
YIN5
U05
Y05
V05
Y15
Y05
Y15
YIN4
U04
Y04
V04
Y14
Y04
Y14
YIN3
U03
Y03
V03
Y13
Y03
Y13
YIN2
U02
Y02
V02
Y12
Y02
Y12
YIN1
U01
Y01
V01
Y11
Y01
Y11
YIN0
U00
Y00
V00
Y10
Y00
Y10
UVIN7
U07
V07
UVIN6
U06
V06
UVIN5
U05
V05
UVIN4
U04
V04
UVIN3
U03
V03
UVIN2
U02
V02
UVIN1
U01
V01
UVIN0
U00
V00
FORMAT
HIN
VIN
YIN
UVIN
00
PAL/NTSC
PAL/NTSC
4:2:2
4:2:2
01 (CCIR 656 only
data)
PAL/NTSC
PAL/NTSC
CCIR 656
x
10
CCIR 656
CCIR 656
CCIR 656
x
11 (full CCIR 656)
x
x
CCIR 656
x



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