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CT1775 Datasheet(PDF) 11 Page - Aeroflex Circuit Technology

Part # CT1775
Description  Universal MacAir/1553 Dumb RTU Hybrid PRELIMINARY DATA SHEET
PDF  14 Pages
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Manufacturer  AEROFLEX [Aeroflex Circuit Technology]
Direct Link  http://www.aeroflex.com
Logo AEROFLEX - Aeroflex Circuit Technology

CT1775 Datasheet(HTML) 11 Page - Aeroflex Circuit Technology

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11
SCDCT1775 Rev B
39
D13
20
-0.2
-12
12
Part of 16 bit parallel tri-state I/O.
40
D11
20
-0.2
-12
12
Part of 16 bit parallel tri-state I/O.
41
D9
20
-0.2
-12
12
Part of 16 bit parallel tri-state I/O.
42
D7
20
-0.2
-12
12
Part of 16 bit parallel tri-state I/O.
43
D5
20
-0.2
-12
12
Part of 16 bit parallel tri-state I/O.
44
D3
20
-0.2
-12
12
Part of 16 bit parallel tri-state I/O.
45
D1
20
-0.2
-12
12
Part of 16 bit parallel tri-state I/O.
46
LOAD DATA 2
20
-0.4
LOW on this input causes the data of the D0 through D7
outputs of the first rank transmit register to be loaded into
the second rank transmit register. A HIGH locks out the
second rank register inputs.
47
+5V
+5V power supply input.
48
+12V
+12Vpower supply input.
49
RX DATA IN
Inverted receiver input.
50
RX STROBE
40
-1.6
A LOW on this input disables the receiver output.
51
TX DATA OUT
Transmitter output.
52
CASE
Case connection.
53
DATA SELECT 2
20
-0.4
A LOW on this input causes the output of the second rank
receiver register to appear on D0 through D7 of the parallel
tri-state I/O.
54
DATA SELECT 1
20
-0.4
A LOW on this input causes the output of the second rank
receiver register to appear on D8 through D15 of the
parallel tri-state I/O.
55
ENA PAR CHECK
20
-0.4
A LOW on this input enables the function of ODD
PARITY.
56
D14
20
-0.2
-12
12
Part of 16 bit parallel tri-state I/O.
57
D12
20
-0.2
-12
12
Part of 16 bit parallel tri-state I/O.
58
D10
20
-0.2
-12
12
Part of 16 bit parallel tri-state I/O.
59
D8
20
-0.2
-12
12
Part of 16 bit parallel tri-state I/O.
60
D6
20
-0.2
-12
12
Part of 16 bit parallel tri-state I/O.
61
D4
20
-0.2
-12
12
Part of 16 bit parallel tri-state I/O.
62
D2
20
-0.2
-12
12
Part of 16 bit parallel tri-state I/O.
63
D0
20
-0.2
-12
12
LSB of 16 bit parallel tri-state I/O.
64
LOAD DATA 1
20
-0.4
A LOW on this input causes the data of the D8 through
D15 outputs of the first rank transmit register to be loaded
into the second rank transmit register. A HIGH locks out
the second rank register inputs.
65
GND
Power supply and logic retum
PIN FUNCTION AND LOADING TABLE (con’t)
PIN
#
NAME
IIH
(µA)
IIL
(mA)
IOH
(mA)
IOL
(mA)
DESCRIPTION



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