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ISO7710

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SLLSER9A – NOVEMBER 2016 – REVISED DECEMBER 2016

Product Folder Links: ISO7710

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Copyright © 2016, Texas Instruments Incorporated

(1)

See the Regulatory Information section for detailed isolation ratings.

8.3 Feature Description

The ISO7710 device is available in two default output state options to enable a variety of application uses.

Table 1 lists the device features.

Table 1. Device Features

PART NUMBER

MAXIMUM DATA

RATE

CHANNEL

DIRECTION

DEFAULT OUTPUT

STATE

PACKAGE

ISO7710

100 Mbps

1 Forward, 0 Reverse

High

DW-16

D-8

ISO7710F

100 Mbps

1 Forward, 0 Reverse

Low

DW-16

D-8

8.3.1 Electromagnetic Compatibility (EMC) Considerations

Many applications in harsh industrial environment are sensitive to disturbances such as electrostatic discharge

(ESD), electrical fast transient (EFT), surge and electromagnetic emissions. These electromagnetic disturbances

are regulated by international standards such as IEC 61000-4-x and CISPR 22. Although system-level

performance and reliability depends, to a large extent, on the application board design and layout, the ISO7710

device incorporates many chip-level design improvements for overall system robustness. Some of these

improvements include:

•

Robust ESD protection cells for input and output signal pins and inter-chip bond pads.

•

Low-resistance connectivity of ESD cells to supply and ground pins.

•

Enhanced performance of high voltage isolation capacitor for better tolerance of ESD, EFT and surge events.

•

Bigger on-chip decoupling capacitors to bypass undesirable high energy signals through a low impedance

path.

•

PMOS and NMOS devices isolated from each other by using guard rings to avoid triggering of parasitic

SCRs.

•

Reduced common mode currents across the isolation barrier by ensuring purely differential internal operation.