VN7140ASTR datasheet(21/55 Pages) STMICROELECTRONICS

21 / 55 page

VN7140AJ, VN7140AS

Electrical specification

DocID027401 Rev 3

21/55

Mode

Conditions

INX

FR(1)

SEn

SELX(1)

OUTX

MultiSense

Comments

See (2)

Outputs

configured for

latch-off(1)

Overload

Overload or

short to GND

causing:

Tj > TTSD or

ΔTj > ΔTj_SD

See (2)

Output cycles

with

temperature

hysteresis

See (2)

Output

latches-off(1)

Undervoltage

VCC < VUSD

(falling)

Hi-Z

Re-start when

VCC > VUSD +

VUSDhyst (rising)

OFF-state

diagnostics

Short to VCC

See (2)

Open-load

See (2)

External pull-

Negative

output

voltage

Inductive

loads turn-off

See (2)

< 0 V

See (2)

Notes:

(1)VN7140AJ only

(2)Refer to Table 11: "MultiSense multiplexer addressing"

Table 11: MultiSense multiplexer addressing

SEn

SEL1

SEL0

MUX channel

MultiSense output

Normal

mode

Overload

OFF-state

diag. (1)

Negative

output

SO-8

N.A.

Hi-Z

N.A.

Channel

diagnostic

ISENSE =

1/K * IOUT

VSENSE =

VSENSEH

VSENSE =

VSENSEH

Hi-Z

PowerSSO-16

Channel

diagnostic

ISENSE =

1/K * IOUT

VSENSE =

VSENSEH

VSENSE =

VSENSEH

Hi-Z

Channel

diagnostic

ISENSE =

1/K * IOUT

VSENSE =

VSENSEH

VSENSE =

VSENSEH

Hi-Z

TCHIP Sense

VSENSE = VSENSE_TC

VCC Sense

VSENSE = VSENSE_VCC

Notes:

(1)In case the output channel corresponding to the selected MUX channel is latched off while the relevant input is

low, Multisense pin delivers feedback according to OFF-State diagnostic. Example 1: FR = 1; IN = 0; OUT = L

(latched); MUX channel = channel 0 diagnostic; Mutisense = 0. Example 2: FR = 1; IN = 0; OUT = latched,

VOUT > VOL; MUX channel = channel 0 diagnostic; Mutisense = VSENSEH

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