IR35201MTYPBF datasheet(32/60 Pages) IRF

32 / 60 page

8+0/7+1/6+2 Dual Output Digital Multi-Phase Controller

IR35201

February 8, 2015 | V1.6

TABLE 20: HIGH-SPEED THRESHOLDS

Function

Hspb_enable

Dedicated bit to enable/disable HSPB.

Resetting this bit will result in the HSPB

function not being activated, regardless of the

error voltage or load oscillation frequency

settings.

Hspb_hth

Error Voltage threshold.

Activates HSPB when the threshold is

exceeded.

0mV – 60mV, 4mV resolution

Hspb_fth

Load Oscillation Frequency Threshold.

Activates HSPB when the load oscillation

frequency is above threshold.

0kHz – 703.5kHz, 46.9kHz resolution.

DYNAMIC VID SLEW RATE

The IR35201 provides the VR designer 16 fast slew

rates each of which can be further configured to 4

different slow slew rates by selecting a slew rate

setting as shown . These slew rates can be further

reduced ½, 1/4, 1/8, and 1/16

TABLE 21: SLEW RATES

mV/

µs

Fast

Rate

x 1/2

Factor

x 1/4

Factor

x 1/8

Factor

x 1/16

Factor

5.0

2.50

1.25

0.0625

7.5

3.75

1.875

0.94

5.00

2.50

1.25

12.5

6.25

3.125

1.56

7.5

3.75

1.88

17.5

8.75

4.375

2.19

5.0

2.5

22.5

11.25

5.625

2.81

12.5

6.25

3.125

27.5

13.75

6.875

3.4375

7.5

3.75

32.5

16.25

8.125

4.0625

17.5

8.75

4.375

42.5

21.25

10.625

5.3125

47.5

23.75

11.875

5.9375

Note: The maximum DVID rate is limited by the inductor

current available to charge the output capacitors. High

DVID rates may not be possible if the output capacitor and

inductor combination does not allow the output voltage to

change at the selected rate.

DYNAMIC VID COMPENSATION

The IR35201 can compensate for the error produced

by the current feedback in a system with AVP (Active

Voltage Positioning) when the output voltage is

ramping to a higher voltage. An output capacitance

term and an AVP bandwidth term are provided in the

MTP registers to help model the effects of variation in

output voltage during a voltage ramp, due to the

inrush current seen by the output bulk capacitors.

Once properly modeled, the output voltage will follow

the DAC more closely during a positive dynamic VID,

and provide better dynamic VID alert timing, as

required by Intel

® processors. Figure 32 shows the

effects that Dynamic VID Compensation has on the

output voltage and the alert timing.

Figure 32: Dynamic VID Compensation

EFFICIENCY SHAPING

In addition to CPU-specified Power States, the

IR35201 features Efficiency Shaping Technology that

enables VR designers to cost-effectively maximize

system efficiency. Efficiency Shaping Technology

consists of Dynamic Phase Control to achieve the

best VR efficiency at a given cost point.

POWER-SAVING STATES

The IR35201 uses Power States to set the power-

savings mode. These are summarized in Table 22.

TABLE 22: POWER STATES

Power

State

Mode

Recommended

Current

DVID COMP ON;

3000uF

DVID COMP OFF

IR35201MTYPBF Datasheet(PDF) 32 Page - International Rectifier

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