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IR35201MTYPBF Datasheet(PDF) 33 Page - International Rectifier |
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IR35201MTYPBF Datasheet(HTML) 33 Page - International Rectifier |
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33 / 60 page ![]() 8+0/7+1/6+2 Dual Output Digital Multi-Phase Controller IR35201 www.irf.com | © 2016 International Rectifier February 8, 2015 | V1.6 33 PS0 Full Power Maximum PS1 Light Load 1-2Φ <20A PS2 1Φ Active Discontinuous (Diode Emulation) <5A PS3 1Φ Passive Discontinuous (Diode Emulation) <1A PS4 Output Voltage DVID or Decay Down to zero depending upon configuration in “ps4_dvid_or_decay” registor. PWM signals of all phases are tristated. Near OFF The Power States may be commanded through I2C/PMBus, the SVID interface, or the IR35201 can autonomously step through the Power States based upon the regulator conditions as summarized in Table 23. PS4 can only be commanded with an SVID command IVID REGISTER IVID efficiency registers are new additions to the family of SVID registers of the IMVP8 specification. When sent an SVID command associated with IVID registers, IR35201 acknowledges the command and stores the received information into the IVID registers. However, IR35201 does not use the information received in IVID registers for any purpose. Instead, it uses the user set-up phase shed function to optimize the VR’s efficiency across the entire operating current range. Table 23: Power State Entry/Exit Command Mode Auto Mode PS1 Entry a) Command n/a if Phase Shed enabled PS1 Exit a) Command to PS0 b) DVID to PS0 c) Current limit to PS0 n/a if Phase Shed enabled PS2 Entry a) Command Current level in 1Φ PS2 Exit a) Command to PS1/0 b) DVID to PS0 c) Current limit to PS0 Fsw > Fsw_desired to PS0, DVID to PS0, Current limit to PS0 PS3 Entry a) Command Current level in 1Φ PS3 Exit a) Command to PS2/1/0 b) DVID to PS0 c) Current limit to PS0 Fsw > Fsw_desired to PS0, DVID to PS0, Current limit to PS0 PS4 Entry a) Command n/a PS4 a) In Single Mode- Any n/a Exit SVID Clock Toggle. b) In Multi Mode – Any SetVID Command . DYNAMIC PHASE CONTROL (DPC) IN PS0 IR35201 optionally supports the ability to autonomously adjust the number of phases with load current, thus optimizing efficiency over a wide range of loads. The output current level at which a phase is added can be programmed individually for each phase for optimum results (Table 24). TABLE 24: DPC THRESHOLDS Register (2A steps) Function Phase1_thresh 2Φ when I > Phase1_thresh Phase2_delta 3Φ when I > Phase1_thresh + Phase2_delta Phase3_delta 4Φ when I > Phase1_thresh + Phase2_delta+Phase3_delta Phase4_delta 5Φ when I > Phase1_thresh + Phase2_delta+Phase3_delta+ Phase4_delta Phase5_delta 6Φ when I > Phase1_thresh + Phase2_delta+Phase3_delta+ Phase4_delta+Phase5_delta Phase6_delta 7Φ and 8Φ when I > Phase1_thresh + Phase2_delta + Phase3_delta + Phase4_delta + Phase5_delta + Phase6_delta As shown in Figure 33 (loop one, 8-phase example shown), the designer can configure the VR to dynamically add or shed phases as the load current varies. Both control loops of the IR35201 have the DPC feature. Figure 33: Dynamic Phase Control Regions - 8Ø Per phase Programmable Threshold for Auto Phase Shed Load Current 3Ø 2Ø 1Ø Programmable Threshold for Auto DCM |
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