LAN89730 datasheet(169/218 Pages) MICROCHIP

169 / 218 page

 2013-2015 Microchip Technology Inc.

DS60001348A-page 169

LAN89730

6.4.6

MII ACCESS REGISTER (MII_ACCESS)

This register is used to control the management cycles to the internal PHY.

Address:

114h

Size:

32 bits

Bits

Description

Type

Default

31:16

RESERVED

15:11

PHY Address

For every access to this register, this field must be set to 00001b.

R/W

00000b

10:6

MII Register Index (MIIRINDA)

These bits select the desired MII register in the PHY.

R/W

00000b

5:2

RESERVED

MII Write (MIIWnR)

Setting this bit tells the PHY that this will be a write operation using the MII

data register. If this bit is not set, this will be a read operation, packing the data

in the MII data register.

R/W

MII Busy (MIIBZY)

This bit must be polled to determine when the MII register access is complete.

This bit must read a logical ‘0’ before writing to this register or to the MII data

read or write any of the MII PHY registers.

During an MII register access, this bit will be set, signifying a read or write

access is in progress. The MII data register must be kept valid until the MAC

clears this bit during a PHY write operation. The MII data register is invalid

until the MAC has cleared this bit during a PHY read operation.

LAN89730 Datasheet(PDF) 169 Page - Microchip Technology