LAN89730 datasheet(171/218 Pages) MICROCHIP

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DS60001348A-page 171

LAN89730

6.4.8

FLOW CONTROL REGISTER (FLOW)

This register is used to control the generation and reception of the Control frames by the MAC’s flow control block.

Before writing to this register, the application has to make sure that the busy bit is not set.

Address:

11Ch

Size:

32 bits

Bits

Description

Type

Default

31:16

Pause Time (FCPT)

This field indicates the value to be used in the PAUSE TIME field in the control

frame.

R/W

0000h

15:3

RESERVED

Pass Control Frames (FCPASS)

When set, the MAC sets the packet filter bit in the receive packet status to

indicate to the application that a valid pause frame has been received. The

application must accept or discard a received frame based on the packet filter

control bit. The MAC receives, decodes and performs the pause function

when a valid pause frame is received in full-duplex mode and when flow con-

trol is enabled (FCEN bit set). When reset, the MAC resets the packet filter bit

in the receive packet status.

The MAC always passes the data of all frames it receives (including flow con-

trol frames) to the application. Frames that do not pass address filtering, as

well as frames with errors, are passed to the application. The application must

discard or retain the received frame’s data based on the received frame’s

STATUS field. Filtering modes (promiscuous mode, for example) take prece-

dence over the FCPASS bit.

R/W

Flow Control Enable (FCEN)

When set, enables the MAC flow control function. The MAC decodes all

incoming frames for control frames; if it receives a valid control frame (PAUSE

command), it disables the transmitter for a specified time (decoded pause

time x slot time). When reset, the MAC flow control function is disabled; the

MAC does not decode frames for control frames.

Note:

Flow Control is applicable when the MAC is set in full-duplex mode.

In half-duplex mode, this bit enables the back pressure function to

control the flow of received frames to the MAC.

R/W

Flow Control Busy (FCBSY)

This bit is set high whenever a pause frame or back pressure is being trans-

mitted. This bit should read logical 0 before writing to the Flow Control

(FLOW) register. During a transfer of Control Frame, this bit continues to be

set, signifying that a frame transmission is in progress. After the PAUSE con-

trol frame's transmission is complete, the MAC resets to 0.

Note:

When writing this register the FCBSY bit must always be zero.

Note:

Applications must always write a zero to this bit.

R/W

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