MCP632 datasheet(22/60 Pages) MICROCHIP

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MCP631/2/3/4/5/9

DS20002197C-page 22

 2009-2014 Microchip Technology Inc.

The power derating across temperature for an op amp

in a particular package can be easily calculated

(assuming equal power dissipations):

EQUATION 4-5:

Several techniques are available to reduce

TJA for a

given POAmax:

• Lower

JA

- Use another package

- PCB layout (ground plane, etc.)

- Heat sinks and air flow

• Reduce POAmax

- Increase RL

- Limit IOUT (using RSER)

- Decrease VDD

4.3

Improving Stability

4.3.1

CAPACITIVE LOADS

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the phase margin (stability) of

the feedback loop decreases and the closed-loop

bandwidth is reduced. This produces gain peaking in

the frequency response, with overshoot and ringing in

the step response. A unity-gain buffer (G = +1) is the

most sensitive to capacitive loads, though all gains

show the same general behavior.

When driving large capacitive loads with these op

amps (e.g., > 20 pF when G = +1), a small series

resistor at the output (RISO in Figure 4-6) improves the

phase margin of the feedback loop by making the

output load resistive at higher frequencies. The

bandwidth will be generally lower than the bandwidth

with no capacitive load.

FIGURE 4-6:

Output Resistor, RISO,

Stabilizes Large Capacitive Loads.

Figure 4-7 gives recommended RISO values for

different capacitive loads and gains. The x-axis is the

normalized load capacitance (CL/GN), where GN is the

circuit’s noise gain. For non-inverting gains, GN and the

Signal Gain are equal. For inverting gains, GN is

1 + |Signal Gain| (e.g., -1 V/V gives GN =+2 V/V).

FIGURE 4-7:

Recommended RISO Values

for Capacitive Loads.

After selecting RISO, double-check the resulting

frequency response peaking and step response

overshoot. Modify the value of RISO until the response

is reasonable. Bench evaluation and simulations with

the MCP631/2/3/4/5/9 SPICE macro model are helpful.

4.3.2

GAIN PEAKING

Figure 4-8 shows an op amp circuit that represents

non-inverting amplifiers (VM is a DC voltage and VP is

the input) or inverting amplifiers (VP is a DC voltage

and VM is the input). The capacitances CN and CG

represent the total capacitance at the input pins; they

include the op amp’s Common-Mode input capacitance

(CCM), board parasitic capacitance and any capacitor

placed in parallel.

FIGURE 4-8:

Amplifier with Parasitic

Capacitance.

CG acts in parallel with RG (except for a gain of +1 V/V),

which causes an increase in gain at high frequencies.

CG also reduces the phase margin of the feedback

loop, which becomes less stable. This effect can be

reduced by either reducing CG or RF.

CN and RN form a low-pass filter that affects the signal

at VP. This filter has a single real pole at 1/(2RNCN).

Where:

TJmax = Absolute maximum junction temperature

OAmax

Jmax

–



--------------------------



RISO

VOUT

MCP63X

100

1,000

1.E-12

1.E-11

1.E-10

1.E-09

1.E-08

Normalized Capacitance; CL/GN (F)

GN = +1

GN  +2

10p

100p

10n

VOUT

MCP63X

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