MGC3030 datasheet(30/50 Pages) MICROCHIP

30 / 50 page

MGC3030/3130

DS40001667D-page 30

Advance Information

 2012-2015 Microchip Technology Inc.

5.5

Communication Interfaces

5.5.1

I2C™

The

MGC3X30

offer

I2C™

interface

for

communicating with an application host. The I2C0 port

offers:

• Slave mode

• Up to 400 kHz

• 7-bit Addressing mode

• Hardware state machine for basic protocol

handling

• Support for repeated start and clock stretching

(Byte mode)

• No multi-master support

I2C™ Hardware Interface

A summary of the hardware interface pins is shown

below in Table 5-5.

•SCL Pin

- The SCL (Serial Clock) pin is electrically

open-drain and requires a pull-up resistor of

typically 1.8 kΩ (for a maximum bus load

capacitance of 200 pF), from SCL to VDD.

- SCL Idle state is high.

•SDA Pin

- The SDA (Serial Data) pin is electrically

open-drain and requires a pull-up resistor of

typically 1.8 kΩ (for a maximum bus load

capacitance of 200 pF), from SDA to VDD.

- SDA Idle state is high.

- Master write data is latched in on SCL rising

edges.

- Master read data is latched out on SCL falling

edges to ensure it is valid during the

subsequent SCL high time.

I2C™ Addressing

The MGC3X30 Device ID 7-bit address is: 0x42

(0b1000010) or 0x43 (0b1000011) depending on the

interface selection pin configuration (IS2+IS1). Please

refer to Table 5-6.

I2C™ Master Read Bit Timing

Master read is to receive position data, gesture reports

and command responses from the MGC3X30. The

timing diagram is shown in Figure 5-4.

• Address bits are latched into the MGC3X30 on

the rising edges of SCL.

• Data bits are latched out of the MGC3X30 on the

rising edges of SCL.

• ACK bit:

- MGC3X30 presents the ACK bit on the ninth

clock for address acknowledgment

-I2C master presents the ACK bit on the ninth

clock for data acknowledgment

•The I2C master must monitor the SCL pin prior to

asserting another clock pulse, as the MGC3X30

may be holding off the I2C master by stretching

the clock.

I2C™ Communication Steps

SCL and SDA lines are Idle high.

I2C master presents Start bit to the MGC3X30

by taking SDA high-to-low, followed by taking

SCL high-to-low.

I2C master presents 7-bit address, followed by a

R/W = 1 (Read mode) bit to the MGC3X30 on

SDA, at the rising edge of eight master clock

(SCL) cycles.

MGC3X30 compares the received address to its

Device ID. If they match, the MGC3X30

acknowledges (ACK) the master sent address

by presenting a low on SDA, followed by a low-

high-low on SCL.

I2C master monitors SCL, as the MGC3X30 may

be clock stretching, holding SCL low to indicate

that the I2C master should wait.

TABLE 5-5:

I2C™ PIN DESCRIPTION

MGC3X30 Pin

Multiplexed Functions

SCL

Serial Clock to Master I2C™

SDA

Serial Data to Master I2C™

TABLE 5-6:

I2C™ DEVICE ID ADDRESS

Device ID Address, 7-bit

000

IS2

TABLE 5-7:

I2C™ DEVICE WRITE ID

ADDRESS (0x84 OR 0x86)

I2C™ Device Write ID Address

0001

IS2

TABLE 5-8:

I2C™ DEVICE READ ID

ADDRESS (0x85 OR 0x87)

I2C™ Device Read ID Address

0001

IS2

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