TLC34075 datasheet(38/52 Pages) TI

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PARAMETER

UNIT

3–6

3.6 Switching Characteristics (Cont’d.)

TL34075-110, TLC34075-135

TLC34075-110

TLC34075-135

MIN

TYP

MAX

MIN

TYP

MAX

SCLK frequency (see Note 10)

MHz

VCLK frequency

MHz

ten1

Enable time, RD low to D<0:7> valid

tdis1

Disable time, RD high to D<0:7> disabled

tv1

Valid time, D<0:7> valid after RD high

tPLH1

Propagation delay, SFLAG/NFLAG

↑ to SCLK

high (see Note 11)

td1

Delay time, RD low to D<0:7> starting to turn

td2

Delay time, selected input clock high/low to

DOTCLK (internal signal) high/low

td3

Delay time, DOTCLK high/low to VCLK

high/low

td4

Delay time, VCLK high/low to SCLK high/low

td5

Delay time, DOTCLK high/low to SCLK

high/low

td6

Delay time, DOTCLK high to IOR/IOG/IOB

active (analog output delay time) (see Note

12)

td7

Analog output settling time (see Note 13)

td8

Delay time, DOTCLK high to HSYNCOUT and

VSYNCOUT valid

tw6

Pulse duration, SCLK high (see Note 11)

Analog output rise time (see Note 14)

Analog output skew

NOTES: 10. SCLK can drive an output capacitive load up to 60 pF. The worst-case transition time between the 10% and

90% levels is less than 4 ns.

11. This parameter applies when the split shift register transfer (SSRT) function is enabled. See Section 2.9.1

for details.

12. Measured from the 90% point of the rising edge of DOTCLK to 50% of the full-scale transition.

13. Measured from the 50% point of the full-scale transition to the point at which the output has settled, within

± 1 LSB (settling time does not include clock and data feedthrough).

14. Measured between 10% and 90% of the full-scale transition.

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