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TLC34075 Datasheet(PDF) 21 Page - Texas Instruments |
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TLC34075 Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 52 page ![]() 2–9 Table 6. Mode and Bus Width Selection MODE MUX CONTROL REGISTER BITS† DATA BITS PER PIXEL‡ PIXEL BUS WIDTH SCLK DIVIDE RATIO§ PIXEL LATCHING SEQUENCE¶ 5 43 210 0# 1 0 1 1 0 1 8 8 1 1) VGA<7:0> 0 1 0 0 0 0 1 4 4 1) P<0> 2) P<1> 3) P<2> 4) P<3> 0 1 0 0 0 1 1 8 8 1) P<0> 2) P<1> 8) P<7> 1 0 1 0 0 1 0 1 16 16 1) P<0> 2) P<1> 16) P<15> 0 1 0 0 1 1 1 32 32 1) P<0> 2) P<1> 32) P<31> 0 1 0 1 0 0 2 4 2 1) P<1:0> 2) P<3:2> 0 1 0 1 0 1 2 8 4 1) P<1:0> 2) P<3:2> 3) P<5:4> 4) P<7:6> 2 0 1 0 1 1 0 2 16 8 1) P<1:0> 2) P<3:2> 8) P<15:14> 0 1 0 1 1 1 2 32 16 1) P<1:0> 2) P<3:2> 16) P<31:30> 0 1 1 0 0 0 4 4 1 1) P<3:0> 0 1 1 0 0 1 4 8 2 1) P<3:0> 2) P<7:4> 3 0 1 1 0 1 0 4 16 4 1) P<3:0> 2) P<7:4> 3) P<11:8> 4) P<15:12> 0 1 1 0 1 1 4 32 8 1) P<3:0> 2) P<7:4> 8) P<31:28> |
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